|
Lines 122-187
static void vgaHWProtect (struct savagef
Link Here
|
| 122 |
} |
122 |
} |
| 123 |
} |
123 |
} |
| 124 |
|
124 |
|
| 125 |
static void vgaHWRestore (struct savagefb_par *par) |
125 |
static void vgaHWRestore (struct savagefb_par *par, struct savage_reg *reg) |
| 126 |
{ |
126 |
{ |
| 127 |
int i; |
127 |
int i; |
| 128 |
|
128 |
|
| 129 |
VGAwMISC (par->MiscOutReg, par); |
129 |
VGAwMISC (reg->MiscOutReg, par); |
| 130 |
|
130 |
|
| 131 |
for (i = 1; i < 5; i++) |
131 |
for (i = 1; i < 5; i++) |
| 132 |
VGAwSEQ (i, par->Sequencer[i], par); |
132 |
VGAwSEQ (i, reg->Sequencer[i], par); |
| 133 |
|
133 |
|
| 134 |
/* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 or |
134 |
/* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 or |
| 135 |
CRTC[17] */ |
135 |
CRTC[17] */ |
| 136 |
VGAwCR (17, par->CRTC[17] & ~0x80, par); |
136 |
VGAwCR (17, reg->CRTC[17] & ~0x80, par); |
| 137 |
|
137 |
|
| 138 |
for (i = 0; i < 25; i++) |
138 |
for (i = 0; i < 25; i++) |
| 139 |
VGAwCR (i, par->CRTC[i], par); |
139 |
VGAwCR (i, reg->CRTC[i], par); |
| 140 |
|
140 |
|
| 141 |
for (i = 0; i < 9; i++) |
141 |
for (i = 0; i < 9; i++) |
| 142 |
VGAwGR (i, par->Graphics[i], par); |
142 |
VGAwGR (i, reg->Graphics[i], par); |
| 143 |
|
143 |
|
| 144 |
VGAenablePalette(par); |
144 |
VGAenablePalette(par); |
| 145 |
|
145 |
|
| 146 |
for (i = 0; i < 21; i++) |
146 |
for (i = 0; i < 21; i++) |
| 147 |
VGAwATTR (i, par->Attribute[i], par); |
147 |
VGAwATTR (i, reg->Attribute[i], par); |
| 148 |
|
148 |
|
| 149 |
VGAdisablePalette(par); |
149 |
VGAdisablePalette(par); |
| 150 |
} |
150 |
} |
| 151 |
|
151 |
|
| 152 |
static void vgaHWInit (struct fb_var_screeninfo *var, |
152 |
static void vgaHWInit (struct fb_var_screeninfo *var, |
| 153 |
struct savagefb_par *par, |
153 |
struct savagefb_par *par, |
| 154 |
struct xtimings *timings) |
154 |
struct xtimings *timings, |
|
|
155 |
struct savage_reg *reg) |
| 155 |
{ |
156 |
{ |
| 156 |
par->MiscOutReg = 0x23; |
157 |
reg->MiscOutReg = 0x23; |
| 157 |
|
158 |
|
| 158 |
if (!(timings->sync & FB_SYNC_HOR_HIGH_ACT)) |
159 |
if (!(timings->sync & FB_SYNC_HOR_HIGH_ACT)) |
| 159 |
par->MiscOutReg |= 0x40; |
160 |
reg->MiscOutReg |= 0x40; |
| 160 |
|
161 |
|
| 161 |
if (!(timings->sync & FB_SYNC_VERT_HIGH_ACT)) |
162 |
if (!(timings->sync & FB_SYNC_VERT_HIGH_ACT)) |
| 162 |
par->MiscOutReg |= 0x80; |
163 |
reg->MiscOutReg |= 0x80; |
| 163 |
|
164 |
|
| 164 |
/* |
165 |
/* |
| 165 |
* Time Sequencer |
166 |
* Time Sequencer |
| 166 |
*/ |
167 |
*/ |
| 167 |
par->Sequencer[0x00] = 0x00; |
168 |
reg->Sequencer[0x00] = 0x00; |
| 168 |
par->Sequencer[0x01] = 0x01; |
169 |
reg->Sequencer[0x01] = 0x01; |
| 169 |
par->Sequencer[0x02] = 0x0F; |
170 |
reg->Sequencer[0x02] = 0x0F; |
| 170 |
par->Sequencer[0x03] = 0x00; /* Font select */ |
171 |
reg->Sequencer[0x03] = 0x00; /* Font select */ |
| 171 |
par->Sequencer[0x04] = 0x0E; /* Misc */ |
172 |
reg->Sequencer[0x04] = 0x0E; /* Misc */ |
| 172 |
|
173 |
|
| 173 |
/* |
174 |
/* |
| 174 |
* CRTC Controller |
175 |
* CRTC Controller |
| 175 |
*/ |
176 |
*/ |
| 176 |
par->CRTC[0x00] = (timings->HTotal >> 3) - 5; |
177 |
reg->CRTC[0x00] = (timings->HTotal >> 3) - 5; |
| 177 |
par->CRTC[0x01] = (timings->HDisplay >> 3) - 1; |
178 |
reg->CRTC[0x01] = (timings->HDisplay >> 3) - 1; |
| 178 |
par->CRTC[0x02] = (timings->HSyncStart >> 3) - 1; |
179 |
reg->CRTC[0x02] = (timings->HSyncStart >> 3) - 1; |
| 179 |
par->CRTC[0x03] = (((timings->HSyncEnd >> 3) - 1) & 0x1f) | 0x80; |
180 |
reg->CRTC[0x03] = (((timings->HSyncEnd >> 3) - 1) & 0x1f) | 0x80; |
| 180 |
par->CRTC[0x04] = (timings->HSyncStart >> 3); |
181 |
reg->CRTC[0x04] = (timings->HSyncStart >> 3); |
| 181 |
par->CRTC[0x05] = ((((timings->HSyncEnd >> 3) - 1) & 0x20) << 2) | |
182 |
reg->CRTC[0x05] = ((((timings->HSyncEnd >> 3) - 1) & 0x20) << 2) | |
| 182 |
(((timings->HSyncEnd >> 3)) & 0x1f); |
183 |
(((timings->HSyncEnd >> 3)) & 0x1f); |
| 183 |
par->CRTC[0x06] = (timings->VTotal - 2) & 0xFF; |
184 |
reg->CRTC[0x06] = (timings->VTotal - 2) & 0xFF; |
| 184 |
par->CRTC[0x07] = (((timings->VTotal - 2) & 0x100) >> 8) | |
185 |
reg->CRTC[0x07] = (((timings->VTotal - 2) & 0x100) >> 8) | |
| 185 |
(((timings->VDisplay - 1) & 0x100) >> 7) | |
186 |
(((timings->VDisplay - 1) & 0x100) >> 7) | |
| 186 |
((timings->VSyncStart & 0x100) >> 6) | |
187 |
((timings->VSyncStart & 0x100) >> 6) | |
| 187 |
(((timings->VSyncStart - 1) & 0x100) >> 5) | |
188 |
(((timings->VSyncStart - 1) & 0x100) >> 5) | |
|
Lines 189-215
static void vgaHWInit (struct fb_var_scr
Link Here
|
| 189 |
(((timings->VTotal - 2) & 0x200) >> 4) | |
190 |
(((timings->VTotal - 2) & 0x200) >> 4) | |
| 190 |
(((timings->VDisplay - 1) & 0x200) >> 3) | |
191 |
(((timings->VDisplay - 1) & 0x200) >> 3) | |
| 191 |
((timings->VSyncStart & 0x200) >> 2); |
192 |
((timings->VSyncStart & 0x200) >> 2); |
| 192 |
par->CRTC[0x08] = 0x00; |
193 |
reg->CRTC[0x08] = 0x00; |
| 193 |
par->CRTC[0x09] = (((timings->VSyncStart - 1) & 0x200) >> 4) | 0x40; |
194 |
reg->CRTC[0x09] = (((timings->VSyncStart - 1) & 0x200) >> 4) | 0x40; |
| 194 |
|
195 |
|
| 195 |
if (timings->dblscan) |
196 |
if (timings->dblscan) |
| 196 |
par->CRTC[0x09] |= 0x80; |
197 |
reg->CRTC[0x09] |= 0x80; |
| 197 |
|
198 |
|
| 198 |
par->CRTC[0x0a] = 0x00; |
199 |
reg->CRTC[0x0a] = 0x00; |
| 199 |
par->CRTC[0x0b] = 0x00; |
200 |
reg->CRTC[0x0b] = 0x00; |
| 200 |
par->CRTC[0x0c] = 0x00; |
201 |
reg->CRTC[0x0c] = 0x00; |
| 201 |
par->CRTC[0x0d] = 0x00; |
202 |
reg->CRTC[0x0d] = 0x00; |
| 202 |
par->CRTC[0x0e] = 0x00; |
203 |
reg->CRTC[0x0e] = 0x00; |
| 203 |
par->CRTC[0x0f] = 0x00; |
204 |
reg->CRTC[0x0f] = 0x00; |
| 204 |
par->CRTC[0x10] = timings->VSyncStart & 0xff; |
205 |
reg->CRTC[0x10] = timings->VSyncStart & 0xff; |
| 205 |
par->CRTC[0x11] = (timings->VSyncEnd & 0x0f) | 0x20; |
206 |
reg->CRTC[0x11] = (timings->VSyncEnd & 0x0f) | 0x20; |
| 206 |
par->CRTC[0x12] = (timings->VDisplay - 1) & 0xff; |
207 |
reg->CRTC[0x12] = (timings->VDisplay - 1) & 0xff; |
| 207 |
par->CRTC[0x13] = var->xres_virtual >> 4; |
208 |
reg->CRTC[0x13] = var->xres_virtual >> 4; |
| 208 |
par->CRTC[0x14] = 0x00; |
209 |
reg->CRTC[0x14] = 0x00; |
| 209 |
par->CRTC[0x15] = (timings->VSyncStart - 1) & 0xff; |
210 |
reg->CRTC[0x15] = (timings->VSyncStart - 1) & 0xff; |
| 210 |
par->CRTC[0x16] = (timings->VSyncEnd - 1) & 0xff; |
211 |
reg->CRTC[0x16] = (timings->VSyncEnd - 1) & 0xff; |
| 211 |
par->CRTC[0x17] = 0xc3; |
212 |
reg->CRTC[0x17] = 0xc3; |
| 212 |
par->CRTC[0x18] = 0xff; |
213 |
reg->CRTC[0x18] = 0xff; |
| 213 |
|
214 |
|
| 214 |
/* |
215 |
/* |
| 215 |
* are these unnecessary? |
216 |
* are these unnecessary? |
|
Lines 220-257
static void vgaHWInit (struct fb_var_scr
Link Here
|
| 220 |
/* |
221 |
/* |
| 221 |
* Graphics Display Controller |
222 |
* Graphics Display Controller |
| 222 |
*/ |
223 |
*/ |
| 223 |
par->Graphics[0x00] = 0x00; |
224 |
reg->Graphics[0x00] = 0x00; |
| 224 |
par->Graphics[0x01] = 0x00; |
225 |
reg->Graphics[0x01] = 0x00; |
| 225 |
par->Graphics[0x02] = 0x00; |
226 |
reg->Graphics[0x02] = 0x00; |
| 226 |
par->Graphics[0x03] = 0x00; |
227 |
reg->Graphics[0x03] = 0x00; |
| 227 |
par->Graphics[0x04] = 0x00; |
228 |
reg->Graphics[0x04] = 0x00; |
| 228 |
par->Graphics[0x05] = 0x40; |
229 |
reg->Graphics[0x05] = 0x40; |
| 229 |
par->Graphics[0x06] = 0x05; /* only map 64k VGA memory !!!! */ |
230 |
reg->Graphics[0x06] = 0x05; /* only map 64k VGA memory !!!! */ |
| 230 |
par->Graphics[0x07] = 0x0F; |
231 |
reg->Graphics[0x07] = 0x0F; |
| 231 |
par->Graphics[0x08] = 0xFF; |
232 |
reg->Graphics[0x08] = 0xFF; |
| 232 |
|
233 |
|
| 233 |
|
234 |
|
| 234 |
par->Attribute[0x00] = 0x00; /* standard colormap translation */ |
235 |
reg->Attribute[0x00] = 0x00; /* standard colormap translation */ |
| 235 |
par->Attribute[0x01] = 0x01; |
236 |
reg->Attribute[0x01] = 0x01; |
| 236 |
par->Attribute[0x02] = 0x02; |
237 |
reg->Attribute[0x02] = 0x02; |
| 237 |
par->Attribute[0x03] = 0x03; |
238 |
reg->Attribute[0x03] = 0x03; |
| 238 |
par->Attribute[0x04] = 0x04; |
239 |
reg->Attribute[0x04] = 0x04; |
| 239 |
par->Attribute[0x05] = 0x05; |
240 |
reg->Attribute[0x05] = 0x05; |
| 240 |
par->Attribute[0x06] = 0x06; |
241 |
reg->Attribute[0x06] = 0x06; |
| 241 |
par->Attribute[0x07] = 0x07; |
242 |
reg->Attribute[0x07] = 0x07; |
| 242 |
par->Attribute[0x08] = 0x08; |
243 |
reg->Attribute[0x08] = 0x08; |
| 243 |
par->Attribute[0x09] = 0x09; |
244 |
reg->Attribute[0x09] = 0x09; |
| 244 |
par->Attribute[0x0a] = 0x0A; |
245 |
reg->Attribute[0x0a] = 0x0A; |
| 245 |
par->Attribute[0x0b] = 0x0B; |
246 |
reg->Attribute[0x0b] = 0x0B; |
| 246 |
par->Attribute[0x0c] = 0x0C; |
247 |
reg->Attribute[0x0c] = 0x0C; |
| 247 |
par->Attribute[0x0d] = 0x0D; |
248 |
reg->Attribute[0x0d] = 0x0D; |
| 248 |
par->Attribute[0x0e] = 0x0E; |
249 |
reg->Attribute[0x0e] = 0x0E; |
| 249 |
par->Attribute[0x0f] = 0x0F; |
250 |
reg->Attribute[0x0f] = 0x0F; |
| 250 |
par->Attribute[0x10] = 0x41; |
251 |
reg->Attribute[0x10] = 0x41; |
| 251 |
par->Attribute[0x11] = 0xFF; |
252 |
reg->Attribute[0x11] = 0xFF; |
| 252 |
par->Attribute[0x12] = 0x0F; |
253 |
reg->Attribute[0x12] = 0x0F; |
| 253 |
par->Attribute[0x13] = 0x00; |
254 |
reg->Attribute[0x13] = 0x00; |
| 254 |
par->Attribute[0x14] = 0x00; |
255 |
reg->Attribute[0x14] = 0x00; |
| 255 |
} |
256 |
} |
| 256 |
|
257 |
|
| 257 |
/* -------------------- Hardware specific routines ------------------------- */ |
258 |
/* -------------------- Hardware specific routines ------------------------- */ |
|
Lines 513-519
static void SavagePrintRegs(void)
Link Here
|
| 513 |
|
514 |
|
| 514 |
/* --------------------------------------------------------------------- */ |
515 |
/* --------------------------------------------------------------------- */ |
| 515 |
|
516 |
|
| 516 |
static void savage_get_default_par(struct savagefb_par *par) |
517 |
static void savage_get_default_par(struct savagefb_par *par, struct savage_reg *reg) |
| 517 |
{ |
518 |
{ |
| 518 |
unsigned char cr3a, cr53, cr66; |
519 |
unsigned char cr3a, cr53, cr66; |
| 519 |
|
520 |
|
|
Lines 543-638
static void savage_get_default_par(struc
Link Here
|
| 543 |
|
544 |
|
| 544 |
/* unlock extended seq regs */ |
545 |
/* unlock extended seq regs */ |
| 545 |
vga_out8 (0x3c4, 0x08, par); |
546 |
vga_out8 (0x3c4, 0x08, par); |
| 546 |
par->SR08 = vga_in8 (0x3c5, par); |
547 |
reg->SR08 = vga_in8 (0x3c5, par); |
| 547 |
vga_out8 (0x3c5, 0x06, par); |
548 |
vga_out8 (0x3c5, 0x06, par); |
| 548 |
|
549 |
|
| 549 |
/* now save all the extended regs we need */ |
550 |
/* now save all the extended regs we need */ |
| 550 |
vga_out8 (0x3d4, 0x31, par); |
551 |
vga_out8 (0x3d4, 0x31, par); |
| 551 |
par->CR31 = vga_in8 (0x3d5, par); |
552 |
reg->CR31 = vga_in8 (0x3d5, par); |
| 552 |
vga_out8 (0x3d4, 0x32, par); |
553 |
vga_out8 (0x3d4, 0x32, par); |
| 553 |
par->CR32 = vga_in8 (0x3d5, par); |
554 |
reg->CR32 = vga_in8 (0x3d5, par); |
| 554 |
vga_out8 (0x3d4, 0x34, par); |
555 |
vga_out8 (0x3d4, 0x34, par); |
| 555 |
par->CR34 = vga_in8 (0x3d5, par); |
556 |
reg->CR34 = vga_in8 (0x3d5, par); |
| 556 |
vga_out8 (0x3d4, 0x36, par); |
557 |
vga_out8 (0x3d4, 0x36, par); |
| 557 |
par->CR36 = vga_in8 (0x3d5, par); |
558 |
reg->CR36 = vga_in8 (0x3d5, par); |
| 558 |
vga_out8 (0x3d4, 0x3a, par); |
559 |
vga_out8 (0x3d4, 0x3a, par); |
| 559 |
par->CR3A = vga_in8 (0x3d5, par); |
560 |
reg->CR3A = vga_in8 (0x3d5, par); |
| 560 |
vga_out8 (0x3d4, 0x40, par); |
561 |
vga_out8 (0x3d4, 0x40, par); |
| 561 |
par->CR40 = vga_in8 (0x3d5, par); |
562 |
reg->CR40 = vga_in8 (0x3d5, par); |
| 562 |
vga_out8 (0x3d4, 0x42, par); |
563 |
vga_out8 (0x3d4, 0x42, par); |
| 563 |
par->CR42 = vga_in8 (0x3d5, par); |
564 |
reg->CR42 = vga_in8 (0x3d5, par); |
| 564 |
vga_out8 (0x3d4, 0x45, par); |
565 |
vga_out8 (0x3d4, 0x45, par); |
| 565 |
par->CR45 = vga_in8 (0x3d5, par); |
566 |
reg->CR45 = vga_in8 (0x3d5, par); |
| 566 |
vga_out8 (0x3d4, 0x50, par); |
567 |
vga_out8 (0x3d4, 0x50, par); |
| 567 |
par->CR50 = vga_in8 (0x3d5, par); |
568 |
reg->CR50 = vga_in8 (0x3d5, par); |
| 568 |
vga_out8 (0x3d4, 0x51, par); |
569 |
vga_out8 (0x3d4, 0x51, par); |
| 569 |
par->CR51 = vga_in8 (0x3d5, par); |
570 |
reg->CR51 = vga_in8 (0x3d5, par); |
| 570 |
vga_out8 (0x3d4, 0x53, par); |
571 |
vga_out8 (0x3d4, 0x53, par); |
| 571 |
par->CR53 = vga_in8 (0x3d5, par); |
572 |
reg->CR53 = vga_in8 (0x3d5, par); |
| 572 |
vga_out8 (0x3d4, 0x58, par); |
573 |
vga_out8 (0x3d4, 0x58, par); |
| 573 |
par->CR58 = vga_in8 (0x3d5, par); |
574 |
reg->CR58 = vga_in8 (0x3d5, par); |
| 574 |
vga_out8 (0x3d4, 0x60, par); |
575 |
vga_out8 (0x3d4, 0x60, par); |
| 575 |
par->CR60 = vga_in8 (0x3d5, par); |
576 |
reg->CR60 = vga_in8 (0x3d5, par); |
| 576 |
vga_out8 (0x3d4, 0x66, par); |
577 |
vga_out8 (0x3d4, 0x66, par); |
| 577 |
par->CR66 = vga_in8 (0x3d5, par); |
578 |
reg->CR66 = vga_in8 (0x3d5, par); |
| 578 |
vga_out8 (0x3d4, 0x67, par); |
579 |
vga_out8 (0x3d4, 0x67, par); |
| 579 |
par->CR67 = vga_in8 (0x3d5, par); |
580 |
reg->CR67 = vga_in8 (0x3d5, par); |
| 580 |
vga_out8 (0x3d4, 0x68, par); |
581 |
vga_out8 (0x3d4, 0x68, par); |
| 581 |
par->CR68 = vga_in8 (0x3d5, par); |
582 |
reg->CR68 = vga_in8 (0x3d5, par); |
| 582 |
vga_out8 (0x3d4, 0x69, par); |
583 |
vga_out8 (0x3d4, 0x69, par); |
| 583 |
par->CR69 = vga_in8 (0x3d5, par); |
584 |
reg->CR69 = vga_in8 (0x3d5, par); |
| 584 |
vga_out8 (0x3d4, 0x6f, par); |
585 |
vga_out8 (0x3d4, 0x6f, par); |
| 585 |
par->CR6F = vga_in8 (0x3d5, par); |
586 |
reg->CR6F = vga_in8 (0x3d5, par); |
| 586 |
|
587 |
|
| 587 |
vga_out8 (0x3d4, 0x33, par); |
588 |
vga_out8 (0x3d4, 0x33, par); |
| 588 |
par->CR33 = vga_in8 (0x3d5, par); |
589 |
reg->CR33 = vga_in8 (0x3d5, par); |
| 589 |
vga_out8 (0x3d4, 0x86, par); |
590 |
vga_out8 (0x3d4, 0x86, par); |
| 590 |
par->CR86 = vga_in8 (0x3d5, par); |
591 |
reg->CR86 = vga_in8 (0x3d5, par); |
| 591 |
vga_out8 (0x3d4, 0x88, par); |
592 |
vga_out8 (0x3d4, 0x88, par); |
| 592 |
par->CR88 = vga_in8 (0x3d5, par); |
593 |
reg->CR88 = vga_in8 (0x3d5, par); |
| 593 |
vga_out8 (0x3d4, 0x90, par); |
594 |
vga_out8 (0x3d4, 0x90, par); |
| 594 |
par->CR90 = vga_in8 (0x3d5, par); |
595 |
reg->CR90 = vga_in8 (0x3d5, par); |
| 595 |
vga_out8 (0x3d4, 0x91, par); |
596 |
vga_out8 (0x3d4, 0x91, par); |
| 596 |
par->CR91 = vga_in8 (0x3d5, par); |
597 |
reg->CR91 = vga_in8 (0x3d5, par); |
| 597 |
vga_out8 (0x3d4, 0xb0, par); |
598 |
vga_out8 (0x3d4, 0xb0, par); |
| 598 |
par->CRB0 = vga_in8 (0x3d5, par) | 0x80; |
599 |
reg->CRB0 = vga_in8 (0x3d5, par) | 0x80; |
| 599 |
|
600 |
|
| 600 |
/* extended mode timing regs */ |
601 |
/* extended mode timing regs */ |
| 601 |
vga_out8 (0x3d4, 0x3b, par); |
602 |
vga_out8 (0x3d4, 0x3b, par); |
| 602 |
par->CR3B = vga_in8 (0x3d5, par); |
603 |
reg->CR3B = vga_in8 (0x3d5, par); |
| 603 |
vga_out8 (0x3d4, 0x3c, par); |
604 |
vga_out8 (0x3d4, 0x3c, par); |
| 604 |
par->CR3C = vga_in8 (0x3d5, par); |
605 |
reg->CR3C = vga_in8 (0x3d5, par); |
| 605 |
vga_out8 (0x3d4, 0x43, par); |
606 |
vga_out8 (0x3d4, 0x43, par); |
| 606 |
par->CR43 = vga_in8 (0x3d5, par); |
607 |
reg->CR43 = vga_in8 (0x3d5, par); |
| 607 |
vga_out8 (0x3d4, 0x5d, par); |
608 |
vga_out8 (0x3d4, 0x5d, par); |
| 608 |
par->CR5D = vga_in8 (0x3d5, par); |
609 |
reg->CR5D = vga_in8 (0x3d5, par); |
| 609 |
vga_out8 (0x3d4, 0x5e, par); |
610 |
vga_out8 (0x3d4, 0x5e, par); |
| 610 |
par->CR5E = vga_in8 (0x3d5, par); |
611 |
reg->CR5E = vga_in8 (0x3d5, par); |
| 611 |
vga_out8 (0x3d4, 0x65, par); |
612 |
vga_out8 (0x3d4, 0x65, par); |
| 612 |
par->CR65 = vga_in8 (0x3d5, par); |
613 |
reg->CR65 = vga_in8 (0x3d5, par); |
| 613 |
|
614 |
|
| 614 |
/* save seq extended regs for DCLK PLL programming */ |
615 |
/* save seq extended regs for DCLK PLL programming */ |
| 615 |
vga_out8 (0x3c4, 0x0e, par); |
616 |
vga_out8 (0x3c4, 0x0e, par); |
| 616 |
par->SR0E = vga_in8 (0x3c5, par); |
617 |
reg->SR0E = vga_in8 (0x3c5, par); |
| 617 |
vga_out8 (0x3c4, 0x0f, par); |
618 |
vga_out8 (0x3c4, 0x0f, par); |
| 618 |
par->SR0F = vga_in8 (0x3c5, par); |
619 |
reg->SR0F = vga_in8 (0x3c5, par); |
| 619 |
vga_out8 (0x3c4, 0x10, par); |
620 |
vga_out8 (0x3c4, 0x10, par); |
| 620 |
par->SR10 = vga_in8 (0x3c5, par); |
621 |
reg->SR10 = vga_in8 (0x3c5, par); |
| 621 |
vga_out8 (0x3c4, 0x11, par); |
622 |
vga_out8 (0x3c4, 0x11, par); |
| 622 |
par->SR11 = vga_in8 (0x3c5, par); |
623 |
reg->SR11 = vga_in8 (0x3c5, par); |
| 623 |
vga_out8 (0x3c4, 0x12, par); |
624 |
vga_out8 (0x3c4, 0x12, par); |
| 624 |
par->SR12 = vga_in8 (0x3c5, par); |
625 |
reg->SR12 = vga_in8 (0x3c5, par); |
| 625 |
vga_out8 (0x3c4, 0x13, par); |
626 |
vga_out8 (0x3c4, 0x13, par); |
| 626 |
par->SR13 = vga_in8 (0x3c5, par); |
627 |
reg->SR13 = vga_in8 (0x3c5, par); |
| 627 |
vga_out8 (0x3c4, 0x29, par); |
628 |
vga_out8 (0x3c4, 0x29, par); |
| 628 |
par->SR29 = vga_in8 (0x3c5, par); |
629 |
reg->SR29 = vga_in8 (0x3c5, par); |
| 629 |
|
630 |
|
| 630 |
vga_out8 (0x3c4, 0x15, par); |
631 |
vga_out8 (0x3c4, 0x15, par); |
| 631 |
par->SR15 = vga_in8 (0x3c5, par); |
632 |
reg->SR15 = vga_in8 (0x3c5, par); |
| 632 |
vga_out8 (0x3c4, 0x30, par); |
633 |
vga_out8 (0x3c4, 0x30, par); |
| 633 |
par->SR30 = vga_in8 (0x3c5, par); |
634 |
reg->SR30 = vga_in8 (0x3c5, par); |
| 634 |
vga_out8 (0x3c4, 0x18, par); |
635 |
vga_out8 (0x3c4, 0x18, par); |
| 635 |
par->SR18 = vga_in8 (0x3c5, par); |
636 |
reg->SR18 = vga_in8 (0x3c5, par); |
| 636 |
|
637 |
|
| 637 |
/* Save flat panel expansion regsters. */ |
638 |
/* Save flat panel expansion regsters. */ |
| 638 |
if (par->chip == S3_SAVAGE_MX) { |
639 |
if (par->chip == S3_SAVAGE_MX) { |
|
Lines 640-646
static void savage_get_default_par(struc
Link Here
|
| 640 |
|
641 |
|
| 641 |
for (i = 0; i < 8; i++) { |
642 |
for (i = 0; i < 8; i++) { |
| 642 |
vga_out8 (0x3c4, 0x54+i, par); |
643 |
vga_out8 (0x3c4, 0x54+i, par); |
| 643 |
par->SR54[i] = vga_in8 (0x3c5, par); |
644 |
reg->SR54[i] = vga_in8 (0x3c5, par); |
| 644 |
} |
645 |
} |
| 645 |
} |
646 |
} |
| 646 |
|
647 |
|
|
Lines 653-662
static void savage_get_default_par(struc
Link Here
|
| 653 |
|
654 |
|
| 654 |
/* now save MIU regs */ |
655 |
/* now save MIU regs */ |
| 655 |
if (par->chip != S3_SAVAGE_MX) { |
656 |
if (par->chip != S3_SAVAGE_MX) { |
| 656 |
par->MMPR0 = savage_in32(FIFO_CONTROL_REG, par); |
657 |
reg->MMPR0 = savage_in32(FIFO_CONTROL_REG, par); |
| 657 |
par->MMPR1 = savage_in32(MIU_CONTROL_REG, par); |
658 |
reg->MMPR1 = savage_in32(MIU_CONTROL_REG, par); |
| 658 |
par->MMPR2 = savage_in32(STREAMS_TIMEOUT_REG, par); |
659 |
reg->MMPR2 = savage_in32(STREAMS_TIMEOUT_REG, par); |
| 659 |
par->MMPR3 = savage_in32(MISC_TIMEOUT_REG, par); |
660 |
reg->MMPR3 = savage_in32(MISC_TIMEOUT_REG, par); |
| 660 |
} |
661 |
} |
| 661 |
|
662 |
|
| 662 |
vga_out8 (0x3d4, 0x3a, par); |
663 |
vga_out8 (0x3d4, 0x3a, par); |
|
Lines 789-795
static int savagefb_check_var (struct fb
Link Here
|
| 789 |
|
790 |
|
| 790 |
|
791 |
|
| 791 |
static int savagefb_decode_var (struct fb_var_screeninfo *var, |
792 |
static int savagefb_decode_var (struct fb_var_screeninfo *var, |
| 792 |
struct savagefb_par *par) |
793 |
struct savagefb_par *par, |
|
|
794 |
struct savage_reg *reg) |
| 793 |
{ |
795 |
{ |
| 794 |
struct xtimings timings; |
796 |
struct xtimings timings; |
| 795 |
int width, dclk, i, j; /*, refresh; */ |
797 |
int width, dclk, i, j; /*, refresh; */ |
|
Lines 831-869
static int savagefb_decode_var (struct f
Link Here
|
| 831 |
* This will allocate the datastructure and initialize all of the |
833 |
* This will allocate the datastructure and initialize all of the |
| 832 |
* generic VGA registers. |
834 |
* generic VGA registers. |
| 833 |
*/ |
835 |
*/ |
| 834 |
vgaHWInit (var, par, &timings); |
836 |
vgaHWInit (var, par, &timings, reg); |
| 835 |
|
837 |
|
| 836 |
/* We need to set CR67 whether or not we use the BIOS. */ |
838 |
/* We need to set CR67 whether or not we use the BIOS. */ |
| 837 |
|
839 |
|
| 838 |
dclk = timings.Clock; |
840 |
dclk = timings.Clock; |
| 839 |
par->CR67 = 0x00; |
841 |
reg->CR67 = 0x00; |
| 840 |
|
842 |
|
| 841 |
switch( var->bits_per_pixel ) { |
843 |
switch( var->bits_per_pixel ) { |
| 842 |
case 8: |
844 |
case 8: |
| 843 |
if( (par->chip == S3_SAVAGE2000) && (dclk >= 230000) ) |
845 |
if( (par->chip == S3_SAVAGE2000) && (dclk >= 230000) ) |
| 844 |
par->CR67 = 0x10; /* 8bpp, 2 pixels/clock */ |
846 |
reg->CR67 = 0x10; /* 8bpp, 2 pixels/clock */ |
| 845 |
else |
847 |
else |
| 846 |
par->CR67 = 0x00; /* 8bpp, 1 pixel/clock */ |
848 |
reg->CR67 = 0x00; /* 8bpp, 1 pixel/clock */ |
| 847 |
break; |
849 |
break; |
| 848 |
case 15: |
850 |
case 15: |
| 849 |
if ( S3_SAVAGE_MOBILE_SERIES(par->chip) || |
851 |
if ( S3_SAVAGE_MOBILE_SERIES(par->chip) || |
| 850 |
((par->chip == S3_SAVAGE2000) && (dclk >= 230000)) ) |
852 |
((par->chip == S3_SAVAGE2000) && (dclk >= 230000)) ) |
| 851 |
par->CR67 = 0x30; /* 15bpp, 2 pixel/clock */ |
853 |
reg->CR67 = 0x30; /* 15bpp, 2 pixel/clock */ |
| 852 |
else |
854 |
else |
| 853 |
par->CR67 = 0x20; /* 15bpp, 1 pixels/clock */ |
855 |
reg->CR67 = 0x20; /* 15bpp, 1 pixels/clock */ |
| 854 |
break; |
856 |
break; |
| 855 |
case 16: |
857 |
case 16: |
| 856 |
if( S3_SAVAGE_MOBILE_SERIES(par->chip) || |
858 |
if( S3_SAVAGE_MOBILE_SERIES(par->chip) || |
| 857 |
((par->chip == S3_SAVAGE2000) && (dclk >= 230000)) ) |
859 |
((par->chip == S3_SAVAGE2000) && (dclk >= 230000)) ) |
| 858 |
par->CR67 = 0x50; /* 16bpp, 2 pixel/clock */ |
860 |
reg->CR67 = 0x50; /* 16bpp, 2 pixel/clock */ |
| 859 |
else |
861 |
else |
| 860 |
par->CR67 = 0x40; /* 16bpp, 1 pixels/clock */ |
862 |
reg->CR67 = 0x40; /* 16bpp, 1 pixels/clock */ |
| 861 |
break; |
863 |
break; |
| 862 |
case 24: |
864 |
case 24: |
| 863 |
par->CR67 = 0x70; |
865 |
reg->CR67 = 0x70; |
| 864 |
break; |
866 |
break; |
| 865 |
case 32: |
867 |
case 32: |
| 866 |
par->CR67 = 0xd0; |
868 |
reg->CR67 = 0xd0; |
| 867 |
break; |
869 |
break; |
| 868 |
} |
870 |
} |
| 869 |
|
871 |
|
|
Lines 875-932
static int savagefb_decode_var (struct f
Link Here
|
| 875 |
vga_out8 (0x3d4, 0x3a, par); |
877 |
vga_out8 (0x3d4, 0x3a, par); |
| 876 |
tmp = vga_in8 (0x3d5, par); |
878 |
tmp = vga_in8 (0x3d5, par); |
| 877 |
if (1 /*FIXME:psav->pci_burst*/) |
879 |
if (1 /*FIXME:psav->pci_burst*/) |
| 878 |
par->CR3A = (tmp & 0x7f) | 0x15; |
880 |
reg->CR3A = (tmp & 0x7f) | 0x15; |
| 879 |
else |
881 |
else |
| 880 |
par->CR3A = tmp | 0x95; |
882 |
reg->CR3A = tmp | 0x95; |
| 881 |
|
883 |
|
| 882 |
par->CR53 = 0x00; |
884 |
reg->CR53 = 0x00; |
| 883 |
par->CR31 = 0x8c; |
885 |
reg->CR31 = 0x8c; |
| 884 |
par->CR66 = 0x89; |
886 |
reg->CR66 = 0x89; |
| 885 |
|
887 |
|
| 886 |
vga_out8 (0x3d4, 0x58, par); |
888 |
vga_out8 (0x3d4, 0x58, par); |
| 887 |
par->CR58 = vga_in8 (0x3d5, par) & 0x80; |
889 |
reg->CR58 = vga_in8 (0x3d5, par) & 0x80; |
| 888 |
par->CR58 |= 0x13; |
890 |
reg->CR58 |= 0x13; |
| 889 |
|
891 |
|
| 890 |
par->SR15 = 0x03 | 0x80; |
892 |
reg->SR15 = 0x03 | 0x80; |
| 891 |
par->SR18 = 0x00; |
893 |
reg->SR18 = 0x00; |
| 892 |
par->CR43 = par->CR45 = par->CR65 = 0x00; |
894 |
reg->CR43 = reg->CR45 = reg->CR65 = 0x00; |
| 893 |
|
895 |
|
| 894 |
vga_out8 (0x3d4, 0x40, par); |
896 |
vga_out8 (0x3d4, 0x40, par); |
| 895 |
par->CR40 = vga_in8 (0x3d5, par) & ~0x01; |
897 |
reg->CR40 = vga_in8 (0x3d5, par) & ~0x01; |
| 896 |
|
898 |
|
| 897 |
par->MMPR0 = 0x010400; |
899 |
reg->MMPR0 = 0x010400; |
| 898 |
par->MMPR1 = 0x00; |
900 |
reg->MMPR1 = 0x00; |
| 899 |
par->MMPR2 = 0x0808; |
901 |
reg->MMPR2 = 0x0808; |
| 900 |
par->MMPR3 = 0x08080810; |
902 |
reg->MMPR3 = 0x08080810; |
| 901 |
|
903 |
|
| 902 |
SavageCalcClock (dclk, 1, 1, 127, 0, 4, 180000, 360000, &m, &n, &r); |
904 |
SavageCalcClock (dclk, 1, 1, 127, 0, 4, 180000, 360000, &m, &n, &r); |
| 903 |
/* m = 107; n = 4; r = 2; */ |
905 |
/* m = 107; n = 4; r = 2; */ |
| 904 |
|
906 |
|
| 905 |
if (par->MCLK <= 0) { |
907 |
if (par->MCLK <= 0) { |
| 906 |
par->SR10 = 255; |
908 |
reg->SR10 = 255; |
| 907 |
par->SR11 = 255; |
909 |
reg->SR11 = 255; |
| 908 |
} else { |
910 |
} else { |
| 909 |
common_calc_clock (par->MCLK, 1, 1, 31, 0, 3, 135000, 270000, |
911 |
common_calc_clock (par->MCLK, 1, 1, 31, 0, 3, 135000, 270000, |
| 910 |
&par->SR11, &par->SR10); |
912 |
®->SR11, ®->SR10); |
| 911 |
/* par->SR10 = 80; // MCLK == 286000 */ |
913 |
/* reg->SR10 = 80; // MCLK == 286000 */ |
| 912 |
/* par->SR11 = 125; */ |
914 |
/* reg->SR11 = 125; */ |
| 913 |
} |
915 |
} |
| 914 |
|
916 |
|
| 915 |
par->SR12 = (r << 6) | (n & 0x3f); |
917 |
reg->SR12 = (r << 6) | (n & 0x3f); |
| 916 |
par->SR13 = m & 0xff; |
918 |
reg->SR13 = m & 0xff; |
| 917 |
par->SR29 = (r & 4) | (m & 0x100) >> 5 | (n & 0x40) >> 2; |
919 |
reg->SR29 = (r & 4) | (m & 0x100) >> 5 | (n & 0x40) >> 2; |
| 918 |
|
920 |
|
| 919 |
if (var->bits_per_pixel < 24) |
921 |
if (var->bits_per_pixel < 24) |
| 920 |
par->MMPR0 -= 0x8000; |
922 |
reg->MMPR0 -= 0x8000; |
| 921 |
else |
923 |
else |
| 922 |
par->MMPR0 -= 0x4000; |
924 |
reg->MMPR0 -= 0x4000; |
| 923 |
|
925 |
|
| 924 |
if (timings.interlaced) |
926 |
if (timings.interlaced) |
| 925 |
par->CR42 = 0x20; |
927 |
reg->CR42 = 0x20; |
| 926 |
else |
928 |
else |
| 927 |
par->CR42 = 0x00; |
929 |
reg->CR42 = 0x00; |
| 928 |
|
930 |
|
| 929 |
par->CR34 = 0x10; /* display fifo */ |
931 |
reg->CR34 = 0x10; /* display fifo */ |
| 930 |
|
932 |
|
| 931 |
i = ((((timings.HTotal >> 3) - 5) & 0x100) >> 8) | |
933 |
i = ((((timings.HTotal >> 3) - 5) & 0x100) >> 8) | |
| 932 |
((((timings.HDisplay >> 3) - 1) & 0x100) >> 7) | |
934 |
((((timings.HDisplay >> 3) - 1) & 0x100) >> 7) | |
|
Lines 938-1014
static int savagefb_decode_var (struct f
Link Here
|
| 938 |
if ((timings.HSyncEnd >> 3) - (timings.HSyncStart >> 3) > 32) |
940 |
if ((timings.HSyncEnd >> 3) - (timings.HSyncStart >> 3) > 32) |
| 939 |
i |= 0x20; |
941 |
i |= 0x20; |
| 940 |
|
942 |
|
| 941 |
j = (par->CRTC[0] + ((i & 0x01) << 8) + |
943 |
j = (reg->CRTC[0] + ((i & 0x01) << 8) + |
| 942 |
par->CRTC[4] + ((i & 0x10) << 4) + 1) / 2; |
944 |
reg->CRTC[4] + ((i & 0x10) << 4) + 1) / 2; |
| 943 |
|
945 |
|
| 944 |
if (j - (par->CRTC[4] + ((i & 0x10) << 4)) < 4) { |
946 |
if (j - (reg->CRTC[4] + ((i & 0x10) << 4)) < 4) { |
| 945 |
if (par->CRTC[4] + ((i & 0x10) << 4) + 4 <= |
947 |
if (reg->CRTC[4] + ((i & 0x10) << 4) + 4 <= |
| 946 |
par->CRTC[0] + ((i & 0x01) << 8)) |
948 |
reg->CRTC[0] + ((i & 0x01) << 8)) |
| 947 |
j = par->CRTC[4] + ((i & 0x10) << 4) + 4; |
949 |
j = reg->CRTC[4] + ((i & 0x10) << 4) + 4; |
| 948 |
else |
950 |
else |
| 949 |
j = par->CRTC[0] + ((i & 0x01) << 8) + 1; |
951 |
j = reg->CRTC[0] + ((i & 0x01) << 8) + 1; |
| 950 |
} |
952 |
} |
| 951 |
|
953 |
|
| 952 |
par->CR3B = j & 0xff; |
954 |
reg->CR3B = j & 0xff; |
| 953 |
i |= (j & 0x100) >> 2; |
955 |
i |= (j & 0x100) >> 2; |
| 954 |
par->CR3C = (par->CRTC[0] + ((i & 0x01) << 8)) / 2; |
956 |
reg->CR3C = (reg->CRTC[0] + ((i & 0x01) << 8)) / 2; |
| 955 |
par->CR5D = i; |
957 |
reg->CR5D = i; |
| 956 |
par->CR5E = (((timings.VTotal - 2) & 0x400) >> 10) | |
958 |
reg->CR5E = (((timings.VTotal - 2) & 0x400) >> 10) | |
| 957 |
(((timings.VDisplay - 1) & 0x400) >> 9) | |
959 |
(((timings.VDisplay - 1) & 0x400) >> 9) | |
| 958 |
(((timings.VSyncStart) & 0x400) >> 8) | |
960 |
(((timings.VSyncStart) & 0x400) >> 8) | |
| 959 |
(((timings.VSyncStart) & 0x400) >> 6) | 0x40; |
961 |
(((timings.VSyncStart) & 0x400) >> 6) | 0x40; |
| 960 |
width = (var->xres_virtual * ((var->bits_per_pixel+7) / 8)) >> 3; |
962 |
width = (var->xres_virtual * ((var->bits_per_pixel+7) / 8)) >> 3; |
| 961 |
par->CR91 = par->CRTC[19] = 0xff & width; |
963 |
reg->CR91 = reg->CRTC[19] = 0xff & width; |
| 962 |
par->CR51 = (0x300 & width) >> 4; |
964 |
reg->CR51 = (0x300 & width) >> 4; |
| 963 |
par->CR90 = 0x80 | (width >> 8); |
965 |
reg->CR90 = 0x80 | (width >> 8); |
| 964 |
par->MiscOutReg |= 0x0c; |
966 |
reg->MiscOutReg |= 0x0c; |
| 965 |
|
967 |
|
| 966 |
/* Set frame buffer description. */ |
968 |
/* Set frame buffer description. */ |
| 967 |
|
969 |
|
| 968 |
if (var->bits_per_pixel <= 8) |
970 |
if (var->bits_per_pixel <= 8) |
| 969 |
par->CR50 = 0; |
971 |
reg->CR50 = 0; |
| 970 |
else if (var->bits_per_pixel <= 16) |
972 |
else if (var->bits_per_pixel <= 16) |
| 971 |
par->CR50 = 0x10; |
973 |
reg->CR50 = 0x10; |
| 972 |
else |
974 |
else |
| 973 |
par->CR50 = 0x30; |
975 |
reg->CR50 = 0x30; |
| 974 |
|
976 |
|
| 975 |
if (var->xres_virtual <= 640) |
977 |
if (var->xres_virtual <= 640) |
| 976 |
par->CR50 |= 0x40; |
978 |
reg->CR50 |= 0x40; |
| 977 |
else if (var->xres_virtual == 800) |
979 |
else if (var->xres_virtual == 800) |
| 978 |
par->CR50 |= 0x80; |
980 |
reg->CR50 |= 0x80; |
| 979 |
else if (var->xres_virtual == 1024) |
981 |
else if (var->xres_virtual == 1024) |
| 980 |
par->CR50 |= 0x00; |
982 |
reg->CR50 |= 0x00; |
| 981 |
else if (var->xres_virtual == 1152) |
983 |
else if (var->xres_virtual == 1152) |
| 982 |
par->CR50 |= 0x01; |
984 |
reg->CR50 |= 0x01; |
| 983 |
else if (var->xres_virtual == 1280) |
985 |
else if (var->xres_virtual == 1280) |
| 984 |
par->CR50 |= 0xc0; |
986 |
reg->CR50 |= 0xc0; |
| 985 |
else if (var->xres_virtual == 1600) |
987 |
else if (var->xres_virtual == 1600) |
| 986 |
par->CR50 |= 0x81; |
988 |
reg->CR50 |= 0x81; |
| 987 |
else |
989 |
else |
| 988 |
par->CR50 |= 0xc1; /* Use GBD */ |
990 |
reg->CR50 |= 0xc1; /* Use GBD */ |
| 989 |
|
991 |
|
| 990 |
if( par->chip == S3_SAVAGE2000 ) |
992 |
if( par->chip == S3_SAVAGE2000 ) |
| 991 |
par->CR33 = 0x08; |
993 |
reg->CR33 = 0x08; |
| 992 |
else |
994 |
else |
| 993 |
par->CR33 = 0x20; |
995 |
reg->CR33 = 0x20; |
| 994 |
|
996 |
|
| 995 |
par->CRTC[0x17] = 0xeb; |
997 |
reg->CRTC[0x17] = 0xeb; |
| 996 |
|
998 |
|
| 997 |
par->CR67 |= 1; |
999 |
reg->CR67 |= 1; |
| 998 |
|
1000 |
|
| 999 |
vga_out8(0x3d4, 0x36, par); |
1001 |
vga_out8(0x3d4, 0x36, par); |
| 1000 |
par->CR36 = vga_in8 (0x3d5, par); |
1002 |
reg->CR36 = vga_in8 (0x3d5, par); |
| 1001 |
vga_out8 (0x3d4, 0x68, par); |
1003 |
vga_out8 (0x3d4, 0x68, par); |
| 1002 |
par->CR68 = vga_in8 (0x3d5, par); |
1004 |
reg->CR68 = vga_in8 (0x3d5, par); |
| 1003 |
par->CR69 = 0; |
1005 |
reg->CR69 = 0; |
| 1004 |
vga_out8 (0x3d4, 0x6f, par); |
1006 |
vga_out8 (0x3d4, 0x6f, par); |
| 1005 |
par->CR6F = vga_in8 (0x3d5, par); |
1007 |
reg->CR6F = vga_in8 (0x3d5, par); |
| 1006 |
vga_out8 (0x3d4, 0x86, par); |
1008 |
vga_out8 (0x3d4, 0x86, par); |
| 1007 |
par->CR86 = vga_in8 (0x3d5, par); |
1009 |
reg->CR86 = vga_in8 (0x3d5, par); |
| 1008 |
vga_out8 (0x3d4, 0x88, par); |
1010 |
vga_out8 (0x3d4, 0x88, par); |
| 1009 |
par->CR88 = vga_in8 (0x3d5, par) | 0x08; |
1011 |
reg->CR88 = vga_in8 (0x3d5, par) | 0x08; |
| 1010 |
vga_out8 (0x3d4, 0xb0, par); |
1012 |
vga_out8 (0x3d4, 0xb0, par); |
| 1011 |
par->CRB0 = vga_in8 (0x3d5, par) | 0x80; |
1013 |
reg->CRB0 = vga_in8 (0x3d5, par) | 0x80; |
| 1012 |
|
1014 |
|
| 1013 |
return 0; |
1015 |
return 0; |
| 1014 |
} |
1016 |
} |
|
Lines 1075-1081
static int savagefb_setcolreg(unsigned
Link Here
|
| 1075 |
return 0; |
1077 |
return 0; |
| 1076 |
} |
1078 |
} |
| 1077 |
|
1079 |
|
| 1078 |
static void savagefb_set_par_int (struct savagefb_par *par) |
1080 |
static void savagefb_set_par_int (struct savagefb_par *par, struct savage_reg *reg) |
| 1079 |
{ |
1081 |
{ |
| 1080 |
unsigned char tmp, cr3a, cr66, cr67; |
1082 |
unsigned char tmp, cr3a, cr66, cr67; |
| 1081 |
|
1083 |
|
|
Lines 1110-1139
static void savagefb_set_par_int (struct
Link Here
|
| 1110 |
|
1112 |
|
| 1111 |
/* restore extended regs */ |
1113 |
/* restore extended regs */ |
| 1112 |
vga_out8 (0x3d4, 0x66, par); |
1114 |
vga_out8 (0x3d4, 0x66, par); |
| 1113 |
vga_out8 (0x3d5, par->CR66, par); |
1115 |
vga_out8 (0x3d5, reg->CR66, par); |
| 1114 |
vga_out8 (0x3d4, 0x3a, par); |
1116 |
vga_out8 (0x3d4, 0x3a, par); |
| 1115 |
vga_out8 (0x3d5, par->CR3A, par); |
1117 |
vga_out8 (0x3d5, reg->CR3A, par); |
| 1116 |
vga_out8 (0x3d4, 0x31, par); |
1118 |
vga_out8 (0x3d4, 0x31, par); |
| 1117 |
vga_out8 (0x3d5, par->CR31, par); |
1119 |
vga_out8 (0x3d5, reg->CR31, par); |
| 1118 |
vga_out8 (0x3d4, 0x32, par); |
1120 |
vga_out8 (0x3d4, 0x32, par); |
| 1119 |
vga_out8 (0x3d5, par->CR32, par); |
1121 |
vga_out8 (0x3d5, reg->CR32, par); |
| 1120 |
vga_out8 (0x3d4, 0x58, par); |
1122 |
vga_out8 (0x3d4, 0x58, par); |
| 1121 |
vga_out8 (0x3d5, par->CR58, par); |
1123 |
vga_out8 (0x3d5, reg->CR58, par); |
| 1122 |
vga_out8 (0x3d4, 0x53, par); |
1124 |
vga_out8 (0x3d4, 0x53, par); |
| 1123 |
vga_out8 (0x3d5, par->CR53 & 0x7f, par); |
1125 |
vga_out8 (0x3d5, reg->CR53 & 0x7f, par); |
| 1124 |
|
1126 |
|
| 1125 |
vga_out16 (0x3c4, 0x0608, par); |
1127 |
vga_out16 (0x3c4, 0x0608, par); |
| 1126 |
|
1128 |
|
| 1127 |
/* Restore DCLK registers. */ |
1129 |
/* Restore DCLK registers. */ |
| 1128 |
|
1130 |
|
| 1129 |
vga_out8 (0x3c4, 0x0e, par); |
1131 |
vga_out8 (0x3c4, 0x0e, par); |
| 1130 |
vga_out8 (0x3c5, par->SR0E, par); |
1132 |
vga_out8 (0x3c5, reg->SR0E, par); |
| 1131 |
vga_out8 (0x3c4, 0x0f, par); |
1133 |
vga_out8 (0x3c4, 0x0f, par); |
| 1132 |
vga_out8 (0x3c5, par->SR0F, par); |
1134 |
vga_out8 (0x3c5, reg->SR0F, par); |
| 1133 |
vga_out8 (0x3c4, 0x29, par); |
1135 |
vga_out8 (0x3c4, 0x29, par); |
| 1134 |
vga_out8 (0x3c5, par->SR29, par); |
1136 |
vga_out8 (0x3c5, reg->SR29, par); |
| 1135 |
vga_out8 (0x3c4, 0x15, par); |
1137 |
vga_out8 (0x3c4, 0x15, par); |
| 1136 |
vga_out8 (0x3c5, par->SR15, par); |
1138 |
vga_out8 (0x3c5, reg->SR15, par); |
| 1137 |
|
1139 |
|
| 1138 |
/* Restore flat panel expansion regsters. */ |
1140 |
/* Restore flat panel expansion regsters. */ |
| 1139 |
if( par->chip == S3_SAVAGE_MX ) { |
1141 |
if( par->chip == S3_SAVAGE_MX ) { |
|
Lines 1141-1167
static void savagefb_set_par_int (struct
Link Here
|
| 1141 |
|
1143 |
|
| 1142 |
for( i = 0; i < 8; i++ ) { |
1144 |
for( i = 0; i < 8; i++ ) { |
| 1143 |
vga_out8 (0x3c4, 0x54+i, par); |
1145 |
vga_out8 (0x3c4, 0x54+i, par); |
| 1144 |
vga_out8 (0x3c5, par->SR54[i], par); |
1146 |
vga_out8 (0x3c5, reg->SR54[i], par); |
| 1145 |
} |
1147 |
} |
| 1146 |
} |
1148 |
} |
| 1147 |
|
1149 |
|
| 1148 |
vgaHWRestore (par); |
1150 |
vgaHWRestore (par, reg); |
| 1149 |
|
1151 |
|
| 1150 |
/* extended mode timing registers */ |
1152 |
/* extended mode timing registers */ |
| 1151 |
vga_out8 (0x3d4, 0x53, par); |
1153 |
vga_out8 (0x3d4, 0x53, par); |
| 1152 |
vga_out8 (0x3d5, par->CR53, par); |
1154 |
vga_out8 (0x3d5, reg->CR53, par); |
| 1153 |
vga_out8 (0x3d4, 0x5d, par); |
1155 |
vga_out8 (0x3d4, 0x5d, par); |
| 1154 |
vga_out8 (0x3d5, par->CR5D, par); |
1156 |
vga_out8 (0x3d5, reg->CR5D, par); |
| 1155 |
vga_out8 (0x3d4, 0x5e, par); |
1157 |
vga_out8 (0x3d4, 0x5e, par); |
| 1156 |
vga_out8 (0x3d5, par->CR5E, par); |
1158 |
vga_out8 (0x3d5, reg->CR5E, par); |
| 1157 |
vga_out8 (0x3d4, 0x3b, par); |
1159 |
vga_out8 (0x3d4, 0x3b, par); |
| 1158 |
vga_out8 (0x3d5, par->CR3B, par); |
1160 |
vga_out8 (0x3d5, reg->CR3B, par); |
| 1159 |
vga_out8 (0x3d4, 0x3c, par); |
1161 |
vga_out8 (0x3d4, 0x3c, par); |
| 1160 |
vga_out8 (0x3d5, par->CR3C, par); |
1162 |
vga_out8 (0x3d5, reg->CR3C, par); |
| 1161 |
vga_out8 (0x3d4, 0x43, par); |
1163 |
vga_out8 (0x3d4, 0x43, par); |
| 1162 |
vga_out8 (0x3d5, par->CR43, par); |
1164 |
vga_out8 (0x3d5, reg->CR43, par); |
| 1163 |
vga_out8 (0x3d4, 0x65, par); |
1165 |
vga_out8 (0x3d4, 0x65, par); |
| 1164 |
vga_out8 (0x3d5, par->CR65, par); |
1166 |
vga_out8 (0x3d5, reg->CR65, par); |
| 1165 |
|
1167 |
|
| 1166 |
/* restore the desired video mode with cr67 */ |
1168 |
/* restore the desired video mode with cr67 */ |
| 1167 |
vga_out8 (0x3d4, 0x67, par); |
1169 |
vga_out8 (0x3d4, 0x67, par); |
|
Lines 1171-1222
static void savagefb_set_par_int (struct
Link Here
|
| 1171 |
udelay (10000); |
1173 |
udelay (10000); |
| 1172 |
vga_out8 (0x3d4, 0x67, par); |
1174 |
vga_out8 (0x3d4, 0x67, par); |
| 1173 |
/* end of part */ |
1175 |
/* end of part */ |
| 1174 |
vga_out8 (0x3d5, par->CR67 & ~0x0c, par); |
1176 |
vga_out8 (0x3d5, reg->CR67 & ~0x0c, par); |
| 1175 |
|
1177 |
|
| 1176 |
/* other mode timing and extended regs */ |
1178 |
/* other mode timing and extended regs */ |
| 1177 |
vga_out8 (0x3d4, 0x34, par); |
1179 |
vga_out8 (0x3d4, 0x34, par); |
| 1178 |
vga_out8 (0x3d5, par->CR34, par); |
1180 |
vga_out8 (0x3d5, reg->CR34, par); |
| 1179 |
vga_out8 (0x3d4, 0x40, par); |
1181 |
vga_out8 (0x3d4, 0x40, par); |
| 1180 |
vga_out8 (0x3d5, par->CR40, par); |
1182 |
vga_out8 (0x3d5, reg->CR40, par); |
| 1181 |
vga_out8 (0x3d4, 0x42, par); |
1183 |
vga_out8 (0x3d4, 0x42, par); |
| 1182 |
vga_out8 (0x3d5, par->CR42, par); |
1184 |
vga_out8 (0x3d5, reg->CR42, par); |
| 1183 |
vga_out8 (0x3d4, 0x45, par); |
1185 |
vga_out8 (0x3d4, 0x45, par); |
| 1184 |
vga_out8 (0x3d5, par->CR45, par); |
1186 |
vga_out8 (0x3d5, reg->CR45, par); |
| 1185 |
vga_out8 (0x3d4, 0x50, par); |
1187 |
vga_out8 (0x3d4, 0x50, par); |
| 1186 |
vga_out8 (0x3d5, par->CR50, par); |
1188 |
vga_out8 (0x3d5, reg->CR50, par); |
| 1187 |
vga_out8 (0x3d4, 0x51, par); |
1189 |
vga_out8 (0x3d4, 0x51, par); |
| 1188 |
vga_out8 (0x3d5, par->CR51, par); |
1190 |
vga_out8 (0x3d5, reg->CR51, par); |
| 1189 |
|
1191 |
|
| 1190 |
/* memory timings */ |
1192 |
/* memory timings */ |
| 1191 |
vga_out8 (0x3d4, 0x36, par); |
1193 |
vga_out8 (0x3d4, 0x36, par); |
| 1192 |
vga_out8 (0x3d5, par->CR36, par); |
1194 |
vga_out8 (0x3d5, reg->CR36, par); |
| 1193 |
vga_out8 (0x3d4, 0x60, par); |
1195 |
vga_out8 (0x3d4, 0x60, par); |
| 1194 |
vga_out8 (0x3d5, par->CR60, par); |
1196 |
vga_out8 (0x3d5, reg->CR60, par); |
| 1195 |
vga_out8 (0x3d4, 0x68, par); |
1197 |
vga_out8 (0x3d4, 0x68, par); |
| 1196 |
vga_out8 (0x3d5, par->CR68, par); |
1198 |
vga_out8 (0x3d5, reg->CR68, par); |
| 1197 |
vga_out8 (0x3d4, 0x69, par); |
1199 |
vga_out8 (0x3d4, 0x69, par); |
| 1198 |
vga_out8 (0x3d5, par->CR69, par); |
1200 |
vga_out8 (0x3d5, reg->CR69, par); |
| 1199 |
vga_out8 (0x3d4, 0x6f, par); |
1201 |
vga_out8 (0x3d4, 0x6f, par); |
| 1200 |
vga_out8 (0x3d5, par->CR6F, par); |
1202 |
vga_out8 (0x3d5, reg->CR6F, par); |
| 1201 |
|
1203 |
|
| 1202 |
vga_out8 (0x3d4, 0x33, par); |
1204 |
vga_out8 (0x3d4, 0x33, par); |
| 1203 |
vga_out8 (0x3d5, par->CR33, par); |
1205 |
vga_out8 (0x3d5, reg->CR33, par); |
| 1204 |
vga_out8 (0x3d4, 0x86, par); |
1206 |
vga_out8 (0x3d4, 0x86, par); |
| 1205 |
vga_out8 (0x3d5, par->CR86, par); |
1207 |
vga_out8 (0x3d5, reg->CR86, par); |
| 1206 |
vga_out8 (0x3d4, 0x88, par); |
1208 |
vga_out8 (0x3d4, 0x88, par); |
| 1207 |
vga_out8 (0x3d5, par->CR88, par); |
1209 |
vga_out8 (0x3d5, reg->CR88, par); |
| 1208 |
vga_out8 (0x3d4, 0x90, par); |
1210 |
vga_out8 (0x3d4, 0x90, par); |
| 1209 |
vga_out8 (0x3d5, par->CR90, par); |
1211 |
vga_out8 (0x3d5, reg->CR90, par); |
| 1210 |
vga_out8 (0x3d4, 0x91, par); |
1212 |
vga_out8 (0x3d4, 0x91, par); |
| 1211 |
vga_out8 (0x3d5, par->CR91, par); |
1213 |
vga_out8 (0x3d5, reg->CR91, par); |
| 1212 |
|
1214 |
|
| 1213 |
if (par->chip == S3_SAVAGE4) { |
1215 |
if (par->chip == S3_SAVAGE4) { |
| 1214 |
vga_out8 (0x3d4, 0xb0, par); |
1216 |
vga_out8 (0x3d4, 0xb0, par); |
| 1215 |
vga_out8 (0x3d5, par->CRB0, par); |
1217 |
vga_out8 (0x3d5, reg->CRB0, par); |
| 1216 |
} |
1218 |
} |
| 1217 |
|
1219 |
|
| 1218 |
vga_out8 (0x3d4, 0x32, par); |
1220 |
vga_out8 (0x3d4, 0x32, par); |
| 1219 |
vga_out8 (0x3d5, par->CR32, par); |
1221 |
vga_out8 (0x3d5, reg->CR32, par); |
| 1220 |
|
1222 |
|
| 1221 |
/* unlock extended seq regs */ |
1223 |
/* unlock extended seq regs */ |
| 1222 |
vga_out8 (0x3c4, 0x08, par); |
1224 |
vga_out8 (0x3c4, 0x08, par); |
|
Lines 1225-1251
static void savagefb_set_par_int (struct
Link Here
|
| 1225 |
/* Restore extended sequencer regs for MCLK. SR10 == 255 indicates |
1227 |
/* Restore extended sequencer regs for MCLK. SR10 == 255 indicates |
| 1226 |
* that we should leave the default SR10 and SR11 values there. |
1228 |
* that we should leave the default SR10 and SR11 values there. |
| 1227 |
*/ |
1229 |
*/ |
| 1228 |
if (par->SR10 != 255) { |
1230 |
if (reg->SR10 != 255) { |
| 1229 |
vga_out8 (0x3c4, 0x10, par); |
1231 |
vga_out8 (0x3c4, 0x10, par); |
| 1230 |
vga_out8 (0x3c5, par->SR10, par); |
1232 |
vga_out8 (0x3c5, reg->SR10, par); |
| 1231 |
vga_out8 (0x3c4, 0x11, par); |
1233 |
vga_out8 (0x3c4, 0x11, par); |
| 1232 |
vga_out8 (0x3c5, par->SR11, par); |
1234 |
vga_out8 (0x3c5, reg->SR11, par); |
| 1233 |
} |
1235 |
} |
| 1234 |
|
1236 |
|
| 1235 |
/* restore extended seq regs for dclk */ |
1237 |
/* restore extended seq regs for dclk */ |
| 1236 |
vga_out8 (0x3c4, 0x0e, par); |
1238 |
vga_out8 (0x3c4, 0x0e, par); |
| 1237 |
vga_out8 (0x3c5, par->SR0E, par); |
1239 |
vga_out8 (0x3c5, reg->SR0E, par); |
| 1238 |
vga_out8 (0x3c4, 0x0f, par); |
1240 |
vga_out8 (0x3c4, 0x0f, par); |
| 1239 |
vga_out8 (0x3c5, par->SR0F, par); |
1241 |
vga_out8 (0x3c5, reg->SR0F, par); |
| 1240 |
vga_out8 (0x3c4, 0x12, par); |
1242 |
vga_out8 (0x3c4, 0x12, par); |
| 1241 |
vga_out8 (0x3c5, par->SR12, par); |
1243 |
vga_out8 (0x3c5, reg->SR12, par); |
| 1242 |
vga_out8 (0x3c4, 0x13, par); |
1244 |
vga_out8 (0x3c4, 0x13, par); |
| 1243 |
vga_out8 (0x3c5, par->SR13, par); |
1245 |
vga_out8 (0x3c5, reg->SR13, par); |
| 1244 |
vga_out8 (0x3c4, 0x29, par); |
1246 |
vga_out8 (0x3c4, 0x29, par); |
| 1245 |
vga_out8 (0x3c5, par->SR29, par); |
1247 |
vga_out8 (0x3c5, reg->SR29, par); |
| 1246 |
|
1248 |
|
| 1247 |
vga_out8 (0x3c4, 0x18, par); |
1249 |
vga_out8 (0x3c4, 0x18, par); |
| 1248 |
vga_out8 (0x3c5, par->SR18, par); |
1250 |
vga_out8 (0x3c5, reg->SR18, par); |
| 1249 |
|
1251 |
|
| 1250 |
/* load new m, n pll values for dclk & mclk */ |
1252 |
/* load new m, n pll values for dclk & mclk */ |
| 1251 |
vga_out8 (0x3c4, 0x15, par); |
1253 |
vga_out8 (0x3c4, 0x15, par); |
|
Lines 1254-1271
static void savagefb_set_par_int (struct
Link Here
|
| 1254 |
vga_out8 (0x3c5, tmp | 0x03, par); |
1256 |
vga_out8 (0x3c5, tmp | 0x03, par); |
| 1255 |
vga_out8 (0x3c5, tmp | 0x23, par); |
1257 |
vga_out8 (0x3c5, tmp | 0x23, par); |
| 1256 |
vga_out8 (0x3c5, tmp | 0x03, par); |
1258 |
vga_out8 (0x3c5, tmp | 0x03, par); |
| 1257 |
vga_out8 (0x3c5, par->SR15, par); |
1259 |
vga_out8 (0x3c5, reg->SR15, par); |
| 1258 |
udelay (100); |
1260 |
udelay (100); |
| 1259 |
|
1261 |
|
| 1260 |
vga_out8 (0x3c4, 0x30, par); |
1262 |
vga_out8 (0x3c4, 0x30, par); |
| 1261 |
vga_out8 (0x3c5, par->SR30, par); |
1263 |
vga_out8 (0x3c5, reg->SR30, par); |
| 1262 |
vga_out8 (0x3c4, 0x08, par); |
1264 |
vga_out8 (0x3c4, 0x08, par); |
| 1263 |
vga_out8 (0x3c5, par->SR08, par); |
1265 |
vga_out8 (0x3c5, reg->SR08, par); |
| 1264 |
|
1266 |
|
| 1265 |
/* now write out cr67 in full, possibly starting STREAMS */ |
1267 |
/* now write out cr67 in full, possibly starting STREAMS */ |
| 1266 |
VerticalRetraceWait(par); |
1268 |
VerticalRetraceWait(par); |
| 1267 |
vga_out8 (0x3d4, 0x67, par); |
1269 |
vga_out8 (0x3d4, 0x67, par); |
| 1268 |
vga_out8 (0x3d5, par->CR67, par); |
1270 |
vga_out8 (0x3d5, reg->CR67, par); |
| 1269 |
|
1271 |
|
| 1270 |
vga_out8 (0x3d4, 0x66, par); |
1272 |
vga_out8 (0x3d4, 0x66, par); |
| 1271 |
cr66 = vga_in8 (0x3d5, par); |
1273 |
cr66 = vga_in8 (0x3d5, par); |
|
Lines 1276-1288
static void savagefb_set_par_int (struct
Link Here
|
| 1276 |
|
1278 |
|
| 1277 |
if (par->chip != S3_SAVAGE_MX) { |
1279 |
if (par->chip != S3_SAVAGE_MX) { |
| 1278 |
VerticalRetraceWait(par); |
1280 |
VerticalRetraceWait(par); |
| 1279 |
savage_out32 (FIFO_CONTROL_REG, par->MMPR0, par); |
1281 |
savage_out32 (FIFO_CONTROL_REG, reg->MMPR0, par); |
| 1280 |
par->SavageWaitIdle (par); |
1282 |
par->SavageWaitIdle (par); |
| 1281 |
savage_out32 (MIU_CONTROL_REG, par->MMPR1, par); |
1283 |
savage_out32 (MIU_CONTROL_REG, reg->MMPR1, par); |
| 1282 |
par->SavageWaitIdle (par); |
1284 |
par->SavageWaitIdle (par); |
| 1283 |
savage_out32 (STREAMS_TIMEOUT_REG, par->MMPR2, par); |
1285 |
savage_out32 (STREAMS_TIMEOUT_REG, reg->MMPR2, par); |
| 1284 |
par->SavageWaitIdle (par); |
1286 |
par->SavageWaitIdle (par); |
| 1285 |
savage_out32 (MISC_TIMEOUT_REG, par->MMPR3, par); |
1287 |
savage_out32 (MISC_TIMEOUT_REG, reg->MMPR3, par); |
| 1286 |
} |
1288 |
} |
| 1287 |
|
1289 |
|
| 1288 |
vga_out8 (0x3d4, 0x66, par); |
1290 |
vga_out8 (0x3d4, 0x66, par); |
|
Lines 1347-1353
static int savagefb_set_par (struct fb_i
Link Here
|
| 1347 |
int err; |
1349 |
int err; |
| 1348 |
|
1350 |
|
| 1349 |
DBG("savagefb_set_par"); |
1351 |
DBG("savagefb_set_par"); |
| 1350 |
err = savagefb_decode_var (var, par); |
1352 |
err = savagefb_decode_var (var, par, &par->state); |
| 1351 |
if (err) |
1353 |
if (err) |
| 1352 |
return err; |
1354 |
return err; |
| 1353 |
|
1355 |
|
|
Lines 1366-1372
static int savagefb_set_par (struct fb_i
Link Here
|
| 1366 |
par->maxClock = par->dacSpeedBpp; |
1368 |
par->maxClock = par->dacSpeedBpp; |
| 1367 |
par->minClock = 10000; |
1369 |
par->minClock = 10000; |
| 1368 |
|
1370 |
|
| 1369 |
savagefb_set_par_int (par); |
1371 |
savagefb_set_par_int (par, &par->state); |
| 1370 |
fb_set_cmap (&info->cmap, info); |
1372 |
fb_set_cmap (&info->cmap, info); |
| 1371 |
savagefb_set_fix(info); |
1373 |
savagefb_set_fix(info); |
| 1372 |
savagefb_set_clip(info); |
1374 |
savagefb_set_clip(info); |
|
Lines 1824-1830
static int __devinit savage_init_hw (str
Link Here
|
| 1824 |
par->display_type = DISP_CRT; |
1826 |
par->display_type = DISP_CRT; |
| 1825 |
} |
1827 |
} |
| 1826 |
|
1828 |
|
| 1827 |
savage_get_default_par (par); |
1829 |
savage_get_default_par (par, &par->state); |
|
|
1830 |
par->save = par->state; |
| 1828 |
|
1831 |
|
| 1829 |
if( S3_SAVAGE4_SERIES(par->chip) ) { |
1832 |
if( S3_SAVAGE4_SERIES(par->chip) ) { |
| 1830 |
/* |
1833 |
/* |