Attachment #51022 for bug #28582

Lines 49-55 module_param_named(powersave, i915_powersave, int, 0600); Link Here

(-)a/drivers/gpu/drm/i915/i915_drv.c (-1 / +1 lines)
49	unsigned int i915_semaphores = 0;	49	unsigned int i915_semaphores = 0;
50	module_param_named(semaphores, i915_semaphores, int, 0600);	50	module_param_named(semaphores, i915_semaphores, int, 0600);
51		51
52	unsigned int i915_enable_rc6 = 0;	52	unsigned int i915_enable_rc6 = 1;
53	module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600);	53	module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600);
54		54
55	unsigned int i915_lvds_downclock = 0;	55	unsigned int i915_lvds_downclock = 0;




#define   DISPLAY_PLANE_A           (0<<20)
#define   DISPLAY_PLANE_B           (1<<20)
#define GFX_OP_PIPE_CONTROL	((0x3<<29)|(0x3<<27)|(0x2<<24)|2)
#define   PIPE_CONTROL_TIMESTAMP	(3<<14)
#define   PIPE_CONTROL_PS_DEPTH_COUNT	(2<<14)
#define   PIPE_CONTROL_QW_WRITE		(1<<14)
#define   PIPE_CONTROL_NO_WRITE		(0<<14)
#define   PIPE_CONTROL_DEPTH_STALL	(1<<13)
#define   PIPE_CONTROL_WC_FLUSH		(1<<12)
#define   PIPE_CONTROL_IS_FLUSH		(1<<11) /* MBZ on Ironlake */
#define   PIPE_CONTROL_TC_FLUSH		(1<<10) /* GM45+ only */
#define   PIPE_CONTROL_ISP_DIS		(1<<9)
#define   PIPE_CONTROL_NOTIFY		(1<<8)
#define   PIPE_CONTROL_GLOBAL_GTT	(1<<2) /* in addr dword */
#define   PIPE_CONTROL_STALL_EN	(1<<1) /* in addr word, Ironlake+ only */






	return 0;
}

#define ILK_RC_PIPECTL_ITERATIONS 1
#define ILK_RC_FLUSH_DWORDS (4 * ILK_RC_PIPECTL_ITERATIONS)

/*
 * Jesse said I needed to do this multiple times. According to the comments in
 * intel_ringbuffer.c, it's only needed for PIPE_NOTIFY. Since we're not using
 * PIPE_NOTIFY anyway, I think we're safe only doing it once.
 */
static void ironlake_rendercache_flush(struct drm_i915_private *dev_priv)
{
	for (i = 0; i < ILK_RC_PIPECTL_ITERATIONS; i++) {
		OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_NO_WRITE |
			 PIPE_CONTROL_WC_FLUSH);
		OUT_RING(0);
		OUT_RING(0);
		OUT_RING(0);
	}
}

void ironlake_enable_rc6(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	 * GPU can automatically power down the render unit if given a page
	 * to save state.
	 */
	ret = BEGIN_LP_RING(10 + ILK_RC_FLUSH_DWORDS);
	if (ret) {
		ironlake_teardown_rc6(dev);
		return;

	OUT_RING(MI_SUSPEND_FLUSH);
	OUT_RING(MI_NOOP);
	OUT_RING(MI_FLUSH);
	ironlake_rendercache_flush(dev_priv);
	OUT_RING(MI_LOAD_REGISTER_IMM(1));
	OUT_RING(PWRCTXA);
	OUT_RING(dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
	OUT_RING(MI_LOAD_REGISTER_IMM(1));
	OUT_RING(RSTDBYCTL);
	OUT_RING(I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
	ADVANCE_LP_RING();

	I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
	I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
}


- 

Return to bug 28582

Lines 228-241 Link Here

(-)a/drivers/gpu/drm/i915/i915_reg.h (-8 / +11 lines)
228	#define DISPLAY_PLANE_A (0<<20)	228	#define DISPLAY_PLANE_A (0<<20)
229	#define DISPLAY_PLANE_B (1<<20)	229	#define DISPLAY_PLANE_B (1<<20)
230	#define GFX_OP_PIPE_CONTROL ((0x3<<29)\|(0x3<<27)\|(0x2<<24)\|2)	230	#define GFX_OP_PIPE_CONTROL ((0x3<<29)\|(0x3<<27)\|(0x2<<24)\|2)
231	#define PIPE_CONTROL_QW_WRITE (1<<14)	231	#define PIPE_CONTROL_TIMESTAMP (3<<14)
232	#define PIPE_CONTROL_DEPTH_STALL (1<<13)	232	#define PIPE_CONTROL_PS_DEPTH_COUNT (2<<14)
233	#define PIPE_CONTROL_WC_FLUSH (1<<12)	233	#define PIPE_CONTROL_QW_WRITE (1<<14)
234	#define PIPE_CONTROL_IS_FLUSH (1<<11) /* MBZ on Ironlake */	234	#define PIPE_CONTROL_NO_WRITE (0<<14)
235	#define PIPE_CONTROL_TC_FLUSH (1<<10) /* GM45+ only */	235	#define PIPE_CONTROL_DEPTH_STALL (1<<13)
236	#define PIPE_CONTROL_ISP_DIS (1<<9)	236	#define PIPE_CONTROL_WC_FLUSH (1<<12)
237	#define PIPE_CONTROL_NOTIFY (1<<8)	237	#define PIPE_CONTROL_IS_FLUSH (1<<11) /* MBZ on Ironlake */
238	#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */	238	#define PIPE_CONTROL_TC_FLUSH (1<<10) /* GM45+ only */
		239	#define PIPE_CONTROL_ISP_DIS (1<<9)
		240	#define PIPE_CONTROL_NOTIFY (1<<8)
		241	#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
239	#define PIPE_CONTROL_STALL_EN (1<<1) /* in addr word, Ironlake+ only */	242	#define PIPE_CONTROL_STALL_EN (1<<1) /* in addr word, Ironlake+ only */
240		243
241		244

Lines 6597-6602 static int ironlake_setup_rc6(struct drm_device *dev) Link Here

(-)a/drivers/gpu/drm/i915/intel_display.c (-5 / +27 lines)
6597	return 0;	6597	return 0;
6598	}	6598	}
6599		6599
		6600	#define ILK_RC_PIPECTL_ITERATIONS 1
		6601	#define ILK_RC_FLUSH_DWORDS (4 * ILK_RC_PIPECTL_ITERATIONS)
		6602
		6603	/*
		6604	* Jesse said I needed to do this multiple times. According to the comments in
		6605	* intel_ringbuffer.c, it's only needed for PIPE_NOTIFY. Since we're not using
		6606	* PIPE_NOTIFY anyway, I think we're safe only doing it once.
		6607	*/
		6608	static void ironlake_rendercache_flush(struct drm_i915_private *dev_priv)
		6609	{
		6610	for (i = 0; i < ILK_RC_PIPECTL_ITERATIONS; i++) {
		6611	OUT_RING(GFX_OP_PIPE_CONTROL \| PIPE_CONTROL_NO_WRITE \|
		6612	PIPE_CONTROL_WC_FLUSH);
		6613	OUT_RING(0);
		6614	OUT_RING(0);
		6615	OUT_RING(0);
		6616	}
		6617	}
		6618
6600	void ironlake_enable_rc6(struct drm_device *dev)	6619	void ironlake_enable_rc6(struct drm_device *dev)
6601	{	6620	{
6602	struct drm_i915_private *dev_priv = dev->dev_private;	6621	struct drm_i915_private *dev_priv = dev->dev_private;
Lines 6616-6622 void ironlake_enable_rc6(struct drm_device *dev) Link Here
6616	* GPU can automatically power down the render unit if given a page	6635	* GPU can automatically power down the render unit if given a page
6617	* to save state.	6636	* to save state.
6618	*/	6637	*/
6619	ret = BEGIN_LP_RING(6);	6638	ret = BEGIN_LP_RING(10 + ILK_RC_FLUSH_DWORDS);
6620	if (ret) {	6639	if (ret) {
6621	ironlake_teardown_rc6(dev);	6640	ironlake_teardown_rc6(dev);
6622	return;	6641	return;
Lines 6632-6641 void ironlake_enable_rc6(struct drm_device *dev) Link Here
6632	OUT_RING(MI_SUSPEND_FLUSH);	6651	OUT_RING(MI_SUSPEND_FLUSH);
6633	OUT_RING(MI_NOOP);	6652	OUT_RING(MI_NOOP);
6634	OUT_RING(MI_FLUSH);	6653	OUT_RING(MI_FLUSH);
		6654	ironlake_rendercache_flush(dev_priv);
		6655	OUT_RING(MI_LOAD_REGISTER_IMM(1));
		6656	OUT_RING(PWRCTXA);
		6657	OUT_RING(dev_priv->pwrctx->gtt_offset \| PWRCTX_EN);
		6658	OUT_RING(MI_LOAD_REGISTER_IMM(1));
		6659	OUT_RING(RSTDBYCTL);
		6660	OUT_RING(I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
6635	ADVANCE_LP_RING();	6661	ADVANCE_LP_RING();
6636
6637	I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset \| PWRCTX_EN);
6638	I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
6639	}	6662	}
6640		6663
6641		6664
6642	-