Lines 698-703
static void i915_audio_component_put_power(struct device *kdev)
Link Here
|
698 |
intel_display_power_put(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO); |
698 |
intel_display_power_put(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO); |
699 |
} |
699 |
} |
700 |
|
700 |
|
|
|
701 |
#define HSW_PWR_WELL_DRIVER _MMIO(0x45404) |
702 |
|
703 |
static int i915_audio_readmisc(struct device *kdev) |
704 |
{ |
705 |
struct drm_i915_private *dev_priv = kdev_to_i915(kdev); |
706 |
uint32_t cdclk_tmp = I915_READ(CDCLK_CTL); |
707 |
uint32_t AudChickenbit = I915_READ(HSW_AUD_CHICKENBIT); |
708 |
uint32_t PwCtl2 = I915_READ(HSW_PWR_WELL_DRIVER); |
709 |
|
710 |
printk("%s %d\n",__func__,__LINE__); |
711 |
printk("%s HSW_AUD_CHICKENBIT=0x%x\n",__func__,AudChickenbit); |
712 |
printk("%s cdclk_ctl =0x%x\n",__func__,cdclk_tmp ); |
713 |
printk("%s cdclk_freq=0x%x\n",__func__, I915_READ(CDCLK_FREQ)); |
714 |
printk("%s PWR_WELL_CTL2 =0x%x\n",__func__, PwCtl2 ); |
715 |
return 0; |
716 |
} |
717 |
|
701 |
static void i915_audio_component_codec_wake_override(struct device *kdev, |
718 |
static void i915_audio_component_codec_wake_override(struct device *kdev, |
702 |
bool enable) |
719 |
bool enable) |
703 |
{ |
720 |
{ |
Lines 868-873
static int i915_audio_component_get_eld(struct device *kdev, int port,
Link Here
|
868 |
.get_cdclk_freq = i915_audio_component_get_cdclk_freq, |
885 |
.get_cdclk_freq = i915_audio_component_get_cdclk_freq, |
869 |
.sync_audio_rate = i915_audio_component_sync_audio_rate, |
886 |
.sync_audio_rate = i915_audio_component_sync_audio_rate, |
870 |
.get_eld = i915_audio_component_get_eld, |
887 |
.get_eld = i915_audio_component_get_eld, |
|
|
888 |
.readmisc = i915_audio_readmisc, |
871 |
}; |
889 |
}; |
872 |
|
890 |
|
873 |
static int i915_audio_component_bind(struct device *i915_kdev, |
891 |
static int i915_audio_component_bind(struct device *i915_kdev, |