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(-)a/drivers/gpu/drm/i915/intel_pm.c (+7 lines)
Lines 4870-4875 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val) Link Here
4870
		break;
4870
		break;
4871
	}
4871
	}
4872
4872
4873
	/* When byt can survive without system hang with dynamic
4874
	 * sw freq adjustments, this restriction can be lifted.
4875
	 */
4876
	if (IS_VALLEYVIEW(dev_priv))
4877
		goto skip_hw_write;
4878
4873
	I915_WRITE(GEN6_RP_UP_EI,
4879
	I915_WRITE(GEN6_RP_UP_EI,
4874
		   GT_INTERVAL_FROM_US(dev_priv, ei_up));
4880
		   GT_INTERVAL_FROM_US(dev_priv, ei_up));
4875
	I915_WRITE(GEN6_RP_UP_THRESHOLD,
4881
	I915_WRITE(GEN6_RP_UP_THRESHOLD,
Lines 4890-4895 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val) Link Here
4890
		   GEN6_RP_UP_BUSY_AVG |
4896
		   GEN6_RP_UP_BUSY_AVG |
4891
		   GEN6_RP_DOWN_IDLE_AVG);
4897
		   GEN6_RP_DOWN_IDLE_AVG);
4892
4898
4899
skip_hw_write:
4893
	dev_priv->rps.power = new_power;
4900
	dev_priv->rps.power = new_power;
4894
	dev_priv->rps.up_threshold = threshold_up;
4901
	dev_priv->rps.up_threshold = threshold_up;
4895
	dev_priv->rps.down_threshold = threshold_down;
4902
	dev_priv->rps.down_threshold = threshold_down;

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