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Lines 175-180
int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
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| 175 |
u16 orig_cmd; |
175 |
u16 orig_cmd; |
| 176 |
struct pci_bus_region region, inverted_region; |
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struct pci_bus_region region, inverted_region; |
| 177 |
bool bar_too_big = false, bar_too_high = false, bar_invalid = false; |
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bool bar_too_big = false, bar_too_high = false, bar_invalid = false; |
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bool bar_readonly = false; |
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mask = type ? PCI_ROM_ADDRESS_MASK : ~0; |
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mask = type ? PCI_ROM_ADDRESS_MASK : ~0; |
| 180 |
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Lines 213-218
int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
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| 213 |
if (type == pci_bar_unknown) { |
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if (type == pci_bar_unknown) { |
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res->flags = decode_bar(dev, l); |
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res->flags = decode_bar(dev, l); |
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res->flags |= IORESOURCE_SIZEALIGN; |
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res->flags |= IORESOURCE_SIZEALIGN; |
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if (l == sz) |
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res->flags |= IORESOURCE_PCI_FIXED; |
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if (res->flags & IORESOURCE_IO) { |
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if (res->flags & IORESOURCE_IO) { |
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l &= PCI_BASE_ADDRESS_IO_MASK; |
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l &= PCI_BASE_ADDRESS_IO_MASK; |
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mask = PCI_BASE_ADDRESS_IO_MASK & (u32) IO_SPACE_LIMIT; |
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mask = PCI_BASE_ADDRESS_IO_MASK & (u32) IO_SPACE_LIMIT; |
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Lines 305-310
out:
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(orig_cmd & PCI_COMMAND_DECODE_ENABLE)) |
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(orig_cmd & PCI_COMMAND_DECODE_ENABLE)) |
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pci_write_config_word(dev, PCI_COMMAND, orig_cmd); |
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pci_write_config_word(dev, PCI_COMMAND, orig_cmd); |
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if (bar_readonly) |
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dev_info(&dev->dev, FW_BUG "reg 0x%x: read-only; can't determine actual size and can't move it\n", |
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pos); |
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if (bar_too_big) |
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if (bar_too_big) |
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dev_err(&dev->dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n", |
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dev_err(&dev->dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n", |
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pos, (unsigned long long) sz64); |
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pos, (unsigned long long) sz64); |