Bug 207685 - [ARM64] different CPU L3 cache size reported by /sys/device/ and dmidecode
Summary: [ARM64] different CPU L3 cache size reported by /sys/device/ and dmidecode
Status: RESOLVED WILL_NOT_FIX
Alias: None
Product: ACPI
Classification: Unclassified
Component: Config-Processors (show other bugs)
Hardware: ARM Linux
: P1 normal
Assignee: acpi_config-processors
URL:
Keywords:
Depends on:
Blocks:
 
Reported: 2020-05-11 06:54 UTC by Aaron Chou
Modified: 2020-05-11 08:41 UTC (History)
0 users

See Also:
Kernel Version: 4.19.90
Subsystem:
Regression: No
Bisected commit-id:


Attachments

Description Aaron Chou 2020-05-11 06:54:03 UTC
In the system, I can get the L3 cache size from two or more ways.

Firstly, I can get it from the kernel interface, such as the `lscpu` command.
Also, I can cat the file `/sys/devices/system/cpu/cpu3/cache/index3/size`.

The way above can give me the L3 cache size is 32768K.

Now if I use the `dmidecode -t cache` command, I get the L3 cache size is 24576K.

And the real size of the L3 cache is 24576K.

Why is it? who can explain it to me?

Thanks.
Comment 1 Aaron Chou 2020-05-11 08:41:27 UTC
ACPI reads these cache information from PPTT. The firmware which populates
the ACPI PPTT must read it from DMI entries and keep them in sync. On
this system, looks like the firmware tried to be more imaginative and
populated PPTT with wrong values. Get that firmware fixed please!

Answered by Sudeep Holla!

Note You need to log in before you can comment on or make changes to this bug.