Bug 12064 - [regression] Measured 688 cycles TSC warp; marking TSC unstable
[regression] Measured 688 cycles TSC warp; marking TSC unstable
Status: CLOSED CODE_FIX
Product: Timers
Classification: Unclassified
Component: Interval Timers
All Linux
: P1 normal
Assigned To: timers_interval-timers
:
Depends on:
Blocks: 11808
  Show dependency treegraph
 
Reported: 2008-11-19 05:05 UTC by Frans Pop
Modified: 2008-11-23 08:33 UTC (History)
2 users (show)

See Also:
Kernel Version: 2.6.28-rc5
Tree: Mainline
Regression: Yes


Attachments
dmesg output for 2.6.28-rc5 (28.28 KB, text/plain)
2008-11-19 05:14 UTC, Frans Pop
Details
kernel config (63.81 KB, text/plain)
2008-11-19 05:14 UTC, Frans Pop
Details

Description Frans Pop 2008-11-19 05:05:35 UTC
Latest working kernel version: 2.6.27
Distribution: Debian
Hardware Environment: Intel desktop with D945GCZ mainboard; Pentium D 3.2GHz
Software Environment: Debian Lenny

Problem Description:
With 2.6.27 I always had the TSC reported stable. With 2.6.28-rc5 I'm seeing
the TSC being consistently marked unstable with a fairly low warp (680-720).

I've not tested intermediate rc releases on this box.
Comment 1 Frans Pop 2008-11-19 05:08:25 UTC
Subject    : [regression] Measured 688 cycles TSC warp; marking TSC unstable
Submitter  : Frans Pop <elendil@planet.nl>
Date       : 2008-11-16 19:27:43
References : http://marc.info/?l=linux-kernel&m=122686370308852&w=2
Comment 2 Frans Pop 2008-11-19 05:14:04 UTC
Created attachment 18943 [details]
dmesg output for 2.6.28-rc5

Relevant diff from dmesg between 2.6.27.4 and 2.6.28-rc5:
-Calibrating delay loop (skipped), value calculated using timer frequency.. 6399.76 BogoMIPS (lpj=12799520)
+HPET: 3 timers in total, 0 timers will be used for per-cpu timer
+Calibrating delay loop (skipped), value calculated using timer frequency.. 6399.73 BogoMIPS (lpj=12799476)
[...]
-ACPI: Core revision 20080609
+ACPI: Core revision 20080926
 Setting APIC routing to flat
 ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
 CPU0: Intel(R) Pentium(R) D CPU 3.20GHz stepping 07
-Using local APIC timer interrupts.
-APIC timer calibration result 12499520
-Detected 12.499 MHz APIC timer.
-Booting processor 1/1 ip 6000
+Booting processor 1 APIC 0x1 ip 0x6000
 Initializing CPU#1
-Calibrating delay using timer specific routine.. 6399.94 BogoMIPS (lpj=12799898)
+Calibrating delay using timer specific routine.. 6198.05 BogoMIPS (lpj=12396107)
[...]
-checking TSC synchronization [CPU#0 -> CPU#1]: passed.
+checking TSC synchronization [CPU#0 -> CPU#1]:
+Measured 696 cycles TSC warp between CPUs, turning off TSC clock.
+Marking TSC unstable due to check_tsc_sync_source failed

Note the rather large difference in BogoMIPS between core 0 and 1.
Comment 3 Frans Pop 2008-11-19 05:14:31 UTC
Created attachment 18944 [details]
kernel config
Comment 4 Rafael J. Wysocki 2008-11-22 13:47:59 UTC
Notify-Also : Thomas Gleixner <tglx@linutronix.de>
Comment 5 Ingo Molnar 2008-11-23 08:33:10 UTC
fixed by:

| commit 93ce99e849433ede4ce8b410b749dc0cad1100b2
| Author: Venki Pallipadi <venkatesh.pallipadi@intel.com>
| Date:   Mon Nov 17 14:43:58 2008 -0800
| 
|    x86: add rdtsc barrier to TSC sync check

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