Bug 9306

Hardware Environment: LPC chip ITE IT8705, mainboard ECS K7S5A, SIS735
Problem Description: 
Low pin controller IT8705 has special function, which sends data from POST port 0x80 (default) to pins of parallel port. This function is default enabled, but BIOS disables it before boot. While booting, kernel probably resets this chip again and doesn't disable POST function. Then all programs, that have outb delay send data to parallel port and make noise on it. This makes PLIP connection works very bad with this chip, but doesn't affect printing (probably beacause printer using handshake wires).


Reference: datasheet page 63 and 64 http://www.alldatasheet.com/datasheet-pdf/pdf/117633/ETC/IT8705F.html


Very simple (and I don't know how it's correct) C source below makes example. It inverts bit disable/enable POST.


/*Program for disabling/enabling IT8705 parallel port POST mode, Petr Cvek, petr.cvek@tul.cz*/

#include <stdio.h>
#include <unistd.h>
#include <asm/io.h>

#define IT8705 0x2e     /*first SuperIO index=0x2e, second SuperIO index=0x4e*/

int write8705(int index,int data)
    {
    outb(index, IT8705);
    usleep(100);
    outb(data, IT8705+1);
    usleep(100);
    return(0);
    }

int read8705(int index)
    {
    outb(index, IT8705);
    usleep(100);
    return(inb(IT8705+1));
    usleep(100);
    }

int main()
    {
/*ALOCATE IT8705 PORTS*/
    if (ioperm(IT8705, 3, 1))
        {
        perror("ioperm");
        exit(1);
        }
    if (ioperm(IT8705+1, 3, 1))
        {
        perror("ioperm");
        exit(1);
        }
/*ENTER IT8705 CONFIG MODE*/
    outb(0x87, IT8705); usleep(100);
    outb(0x01, IT8705); usleep(100);
    outb(0x55, IT8705); usleep(100);
    if (IT8705==0x2e)
        {
        outb(0x55, IT8705);
        usleep(100);
        printf("First SuperIO\n");
        }
    else if (IT8705==0x4e)
        {
        outb(0xaa, IT8705);
        usleep(100);
        printf("Second SuperIO\n");
        }
/*POINT TO PART OF IT8705 TO BE MODIFICATED*/
    write8705(0x7, 0x3);        /*parport*/
/*READ DATA BEFORE CHANGE*/
    printf("Parport config reg before change: %d\n", read8705(0xf0));
/*PARALEL PORT CONFIG ENABLE/DISABLE POST ON PARPORT*/
    write8705(0xf0,(read8705(0xf0) + 0x8)); /*bit 3 POST, bits 4-7 reserved*/
/*READ DATA AFTER CHANGE*/
    printf("Parport config reg after change: %d\n", read8705(0xf0));
/*EXIT CONFIG MODE*/
    write8705(0x2,0x2);
/*UNALOCATE IT8705 PORTS*/
    if (ioperm(IT8705+1, 3, 0))
        {
        perror("ioperm");
        exit(1);
        }
    if (ioperm(IT8705, 3, 0))
        {
        perror("ioperm");
        exit(1);
        }
/*END*/
    exit(0);
    }