Bug 29502
| Summary: | Change to legacy algo to preferring lower post dividers breaks certain modelines | ||
|---|---|---|---|
| Product: | Drivers | Reporter: | Chris Kennedy (bitbytebit) |
| Component: | Video(DRI - non Intel) | Assignee: | drivers_video-dri |
| Status: | CLOSED CODE_FIX | ||
| Severity: | normal | CC: | florian, maciej.rutecki, rjw |
| Priority: | P1 | ||
| Hardware: | All | ||
| OS: | Linux | ||
| Kernel Version: | 2.6.38-rc5 | Subsystem: | |
| Regression: | Yes | Bisected commit-id: | |
| Bug Depends on: | |||
| Bug Blocks: | 27352 | ||
| Attachments: | revert | ||
On the above entry, I meant that it works in 2.6.38-rc3 or before the patch that included the change above with the legacy algo lower post divider change. Created attachment 48532 [details]
revert
revert that patch. It's not needed any more as the bugs it originally fixed were fixed via an alternate method.
Great, reverting works. Thanks, Chris Patch : https://bugzilla.kernel.org/attachment.cgi?id=48532 Handled-By : Alex Deucher <alexdeucher@gmail.com> merged in .38-rc7: commit bd6a60afeb4c9ada3ff27f1d13db1a2b5c11d8c0 Author: Alex Deucher <alexdeucher@gmail.com> Date: Mon Feb 21 01:11:59 2011 -0500 Revert "drm/radeon/kms: switch back to min->max pll post divider iteration" This reverts commit a6f9761743bf35b052180f4a8bdae4d2cc0465f6. |
There's an issue with some legacy chips plus low dotclocks in the 2.6.38-rc5 kernel, This is the change/patch that broke them. Reverting this patch, they work as they did before... "Also, switch the legacy algo back to preferring lower post dividers." @@ -849,7 +951,7 @@ void radeon_compute_pll(struct radeon_pll *pll, max_fractional_feed_div = pll->max_frac_feedback_div; } - for (post_div = max_post_div; post_div >= min_post_div; --post_div) { + for (post_div = min_post_div; post_div <= max_post_div; ++post_div) { uint32_t ref_div; if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) A person has a ATI Radeon 9200SE 5964 (AGP)and with 2.6.38-rc4-git4+ it works while with 2.6.38-rc5 there are certain (not all) modelines with low dotclocks that end up being totally out of sync. Here's an example of a non-working modeline for him with the newer kernel, vs. the older one step back before the patch with the above change... # toki 256x224@59.61 15.6774Khz ModeLine "256x224x59.61" 5.518455 256 272 304 352 224 235 238 263 -HSync -VSync There's a lot of other ones thought that can work with the same lower dotclocks, so I'm not sure why that is, he tested that change with the legacy pll computation reversed back to how it was and now works again with modelines like the above. Thanks, Chris