Bug 206587
| Summary: | x86/mce: Do not log spurious corrected mce errors | ||
|---|---|---|---|
| Product: | Platform Specific/Hardware | Reporter: | Prarit Bhargava (prarit) |
| Component: | x86-64 | Assignee: | platform_x86_64 (platform_x86_64) |
| Status: | RESOLVED CODE_FIX | ||
| Severity: | normal | CC: | bp |
| Priority: | P1 | ||
| Hardware: | x86-64 | ||
| OS: | Linux | ||
| Kernel Version: | 5.6-rc2 | Subsystem: | |
| Regression: | No | Bisected commit-id: | |
| Attachments: |
4th gen core family mobile specificatoin update
$th gen core family desktop specification update 5th gen core family spec update xeon e3 1200v3 spec update |
||
Created attachment 287461 [details]
4th gen core family mobile specificatoin update
Created attachment 287463 [details]
$th gen core family desktop specification update
Created attachment 287465 [details]
5th gen core family spec update
Created attachment 287467 [details]
xeon e3 1200v3 spec update
Is this one still relevant or can we close? Yes, fixed in 2976908e4198 ("x86/mce: Do not log spurious corrected mce errors")
P.
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A user has reported that they are seeing spurious corrected errors on their hardware. Intel Errata HSD131, HSM142, HSW131, and BDM48 report that "spurious corrected errors may be logged in the IA32_MC0_STATUS register with the valid field (bit 63) set, the uncorrected error field (bit 61) not set, a Model Specific Error Code (bits [31:16]) of 0x000F, and an MCA Error Code (bits [15:0]) of 0x0005." Block these spurious errors from the console and logs. Links to Intel Specification updates: HSD131: https://www.intel.com/content/www/us/en/products/docs/processors/core/4th-gen-core-family-desktop-specification-update.html HSM142: https://www.intel.com/content/www/us/en/products/docs/processors/core/4th-gen-core-family-mobile-specification-update.html HSW131: https://www.intel.com/content/www/us/en/processors/xeon/xeon-e3-1200v3-spec-update.html BDM48: https://www.intel.com/content/www/us/en/products/docs/processors/core/5th-gen-core-family-spec-update.html P.