Bug 198057

Created attachment 260993 [details]
lspci -vv

Background information from Christian:

> The CPU is a PA Semi “PWRficient” PA6T-1682M. This device combines dual
> 1.8GHz PowerPC cores with a 2MB L2 cache, dual channel DDR2 memory
> controllers and 24 SerDes channels. The PowerPC cores adhere to the
> Power ISA v2.04, and support 64-bit extensions. They feature a double
> precision FPU and a VMX (AltiVec) vector unit. They each have a 64kB
> I-cache and a 64kB D-cache.  The SerDes channels support PCI Express,
> XAUI and SGMII protocols. The “ENVOI” I/O subsystem which drives them
> includes caching, offload and DMA resources to maximise I/O
> performance.

> Nemo uses the AMD/ATI SB600 South Bridge to provide various integrated
> I/O functions including SATA/PATA ports, USB and audio. The SB600
> connects to the CPU via a PCIe x4 link. This is termed an “A-Link II
> Express” link by ATI/AMD. The design team determined early in the
> development of Nemo that the link’s behaviour as an endpoint does not
> comply fully with the PCI Express specification. Specifically, it
> requires the root complex to use non-zero device numbers in type 0
> configuration cycles to enumerate all the devices within the SB600.
> This is related to the PC architecture and is used to allow SB600
> devices appear on logical bus 0.

> More information about the Nemo board:

>   https://en.wikipedia.org/wiki/AmigaOne_X1000
>   http://www.a-eon.com/?page=x1000
>   http://www.amigaos.net/hardware/35/amigaone-x1000

pci 0000:00:11.0: [1959:a002] type 01 class 0x060400
pci 0000:00:11.0: PCI bridge to [bus 05-06] (Root Port)
pci 0000:05:12.0: [1002:4380] type 00 class 0x01018f
pci 0000:05:13.0: [1002:4387] type 00 class 0x0c0310
...

00:11.0 claims to be a PCIe Root Port leading to [bus 05-06].  That
means there's a Link (presumably this A-Link II Express thing), and the
downstream end of the Link *should* be a PCIe Upstream Port on bus 05,
but no such device is visible.  I suppose the SB600 does implement
some sort of PCIe Port there, but keeps it invisible to software, and
at the same time, contains an invisible bridge that connects the Link
to all the conventional PCI devices on bus 05.

When we scan bus 05, we do this:

  pci_scan_child_bus_extend(bus=05)
    for (devfn = 0; devfn < 0x100; devfn += 8)
      pci_scan_slot(05, 00.0)
        pci_scan_single_device
          pci_scan_device(05, 00.0)           # fails; no 05:00.0
      pci_scan_slot(05, 01.0)
        only_one_child(bus=05)
          parent = 00:11.0
          pci_pcie_type(00:11.0) == ROOT_PORT # returns true

Since only_one_child() sees that 00:11.0 is a Root Port, we give up
before we even get to the PCI_SCAN_ALL_PCIE_DEVS test.