Bug 16636

Summary: The boot process freezes and needs keyboard input to continue - Bisected to Commit 988888c, bootup hangs
Product: Platform Specific/Hardware Reporter: Larry Finger (Larry.Finger)
Component: x86-64Assignee: platform_x86_64 (platform_x86_64)
Status: CLOSED CODE_FIX    
Severity: high CC: rjw
Priority: P1    
Hardware: All   
OS: Linux   
Kernel Version: 2.6.36-rc1 Subsystem:
Regression: Yes Bisected commit-id:

Description Larry Finger 2010-08-20 00:22:00 UTC
My x86_64 system with an AMD Turion 64 X2 TL-60 CPU pauses/freezes as soon as the kernel is loaded during boot. It will only proceed if some key is pressed and stops many times. I have never stayed with it, thus it may run OK once booted.

The problem was bisected to:

commit 9d8888c2a214aece2494a49e699a097c2ba9498b
Author: Hans Rosenfeld <hans.rosenfeld@amd.com>
Date:   Wed Jul 28 19:09:31 2010 +0200

    x86, cpu: Clean up AMD erratum 400 workaround
    
    Remove check_c1e_idle() and use the new AMD errata checking framework
    instead.
    
    Signed-off-by: Hans Rosenfeld <hans.rosenfeld@amd.com>
    LKML-Reference: <1280336972-865982-2-git-send-email-hans.rosenfeld@amd.com>
    Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>

----- /proc/cpuinfo -----
  processor     : 0
  vendor_id     : AuthenticAMD
  cpu family    : 15
  model         : 104
  model name    : AMD Turion(tm) 64 X2 TL-60
  stepping      : 2
  cpu MHz               : 2000.000
  cache size    : 512 KB
  physical id   : 0
  siblings      : 2
  core id               : 0
  cpu cores     : 2
  apicid                : 0
  initial apicid        : 0
  fpu           : yes
  fpu_exception : yes
  cpuid level   : 1
  wp            : yes
  flags         : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt rdtscp lm 3dnowext 3dnow rep_good extd_apicid pni cx16 lahf_lm cmp_legacy svm extapic cr8_legacy 3dnowprefetch lbrv
  bogomips      : 4000.93
  TLB size      : 1024 4K pages
  clflush size  : 64
  cache_alignment       : 64
  address sizes : 40 bits physical, 48 bits virtual
  power management: ts fid vid ttp tm stc 100mhzsteps
 
CPU #1 is the same.
Comment 1 Larry Finger 2010-08-20 13:55:56 UTC
This issue is fixed by the patch at
http://git.kernel.org/tip/07a7795ca2e6e66d00b184efb46bd0e23d90d3fe.