diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index c9084dedfcfa..a4156753cd8b 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -342,6 +342,7 @@
 
 /* Fam 17h MSRs */
 #define MSR_F17H_IRPERF			0xc00000e9
+#define MSR_F17H_PACKAGE_CSTATE		0xc0010292
 
 /* Fam 16h MSRs */
 #define MSR_F16H_L2I_PERF_CTL		0xc0010230
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index f0e6456ca7d3..c0dc04cf026b 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -791,12 +791,22 @@ static void init_amd_bd(struct cpuinfo_x86 *c)
 
 static void init_amd_zn(struct cpuinfo_x86 *c)
 {
+	u64 value;
+
 	/*
 	 * Fix erratum 1076: CPB feature bit not being set in CPUID. It affects
 	 * all up to and including B1.
 	 */
 	if (c->x86_model <= 1 && c->x86_stepping <= 1)
 		set_cpu_cap(c, X86_FEATURE_CPB);
+
+	if (c->x86_model <= 1) {
+		if (!rdmsrl_safe(MSR_F17H_PACKAGE_CSTATE, &value) && (value & BIT_64(32))) {
+			value &= ~BIT_64(32);
+			if (!wrmsrl_safe(MSR_F17H_PACKAGE_CSTATE, value))
+				pr_info_once("CPU: Disable Package C-State.\n");
+		}
+	}
 }
 
 static void init_amd(struct cpuinfo_x86 *c)