*** drivers/gpu/drm/i915/intel_dp.c.virgin	2013-06-16 00:51:07.000000000 +0300
--- drivers/gpu/drm/i915/intel_dp.c	2013-06-18 22:48:19.276151283 +0300
***************
*** 702,709 ****
  	/* Walk through all bpp values. Luckily they're all nicely spaced with 2
  	 * bpc in between. */
  	bpp = min_t(int, 8*3, pipe_config->pipe_bpp);
- 	if (is_edp(intel_dp) && dev_priv->edp.bpp)
- 		bpp = min_t(int, bpp, dev_priv->edp.bpp);
  
  	for (; bpp >= 6*3; bpp -= 2*3) {
  		mode_rate = intel_dp_link_required(target_clock, bpp);
--- 702,707 ----
***************
*** 742,748 ****
  	intel_dp->link_bw = bws[clock];
  	intel_dp->lane_count = lane_count;
  	adjusted_mode->clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
- 	pipe_config->pipe_bpp = bpp;
  	pipe_config->pixel_target_clock = target_clock;
  
  	DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
--- 740,745 ----
***************
*** 755,760 ****
--- 752,761 ----
  			       target_clock, adjusted_mode->clock,
  			       &pipe_config->dp_m_n);
  
+ 	if (is_edp(intel_dp) && dev_priv->edp.bpp)
+ 		bpp = min_t(int, bpp, dev_priv->edp.bpp);
+ 	pipe_config->pipe_bpp = bpp;
+ 
  	return true;
  }