arch/ppc/boot/images/zImage.elf:     file format elf32-powerpc

  400154:	4e 80 00 20 	blr
 */
void __attribute__ ((weak))
embed_config(bd_t **bdp)
{
}
  400158:	4e 80 00 20 	blr

0040015c <load_kernel>:

unsigned long
load_kernel(unsigned long load_addr, int num_words, unsigned long cksum, bd_t *bp)
{
  40015c:	94 21 ff c0 	stwu    r1,-64(r1)
  400160:	7c 08 02 a6 	mflr    r0
  400164:	bf 01 00 20 	stmw    r24,32(r1)
  400168:	7c 7d 1b 78 	mr      r29,r3
  40016c:	7c 9c 23 78 	mr      r28,r4
	char *cp, ch;
	int timer = 0, zimage_size;
	unsigned long initrd_size;
	/* First initialize the serial console port.   Then
	 * capture the embedded board information.
	 */
#if defined(CONFIG_SERIAL_CPM_CONSOLE) || defined(CONFIG_SERIAL_8250_CONSOLE)
	com_port = serial_init(0, 0);
  400170:	38 60 00 00 	li      r3,0
  400174:	38 80 00 00 	li      r4,0
  400178:	90 01 00 44 	stw     r0,68(r1)
#endif

        bp = hold_residual;
  40017c:	3f 40 00 40 	lis     r26,64
  400180:	48 00 10 69 	bl      4011e8 <serial_init>
  400184:	3d 20 00 4d 	lis     r9,77
  400188:	90 69 50 0c 	stw     r3,20492(r9)
  40018c:	83 da 40 80 	lwz     r30,16512(r26)
	embed_config(&bp);

	/* Grab some space for the command line and board info.  Since
	 * we no longer use the ELF header, but it was loaded, grab
	 * that space.
	 */
#ifdef CONFIG_MBX
	/* Because of the way the MBX loads the ELF image, we can't
	 * tell where we started.  We read a magic variable from the NVRAM
	 * that gives us the intermediate buffer load address.
	 */
	load_addr = *(uint *)0xfa000020;
	load_addr += 0x10000;		/* Skip ELF header */
#endif
	/* copy board data */
//	if (bp)
//		memcpy(hold_residual,bp,sizeof(bd_t));

	/* Set end of memory available to us.  It is always the highest
	 * memory address provided by the board information.
	 */
	end_avail = (char *)(bp->bi_memsize);

	puts("\nloaded at:     "); puthex(load_addr);
  400190:	3c 60 00 40 	lis     r3,64

.......................................

004005c0 <embed_config>:
	 * - If the data cache is turned on this must have been done by
	 *   a bootloader and we assume that the cache contents are
	 *   valid.
	 */
	__asm__("mfdccr %0": "=r" (dccr));
  4005c0:	7c 1a fa a6 	mfdccr  r0
	if (dccr == 0) {
  4005c4:	2f 80 00 00 	cmpwi   cr7,r0,0
  4005c8:	80 63 00 00 	lwz     r3,0(r3)
  4005cc:	40 9e 00 1c 	bne-    cr7,4005e8 <embed_config+0x28>
  4005d0:	38 00 01 00 	li      r0,256
  4005d4:	7c 09 03 a6 	mtctr   r0
  4005d8:	39 20 00 00 	li      r9,0
		for (addr = 0;
		     addr < (congruence_classes * line_size);
		     addr += line_size) {
			__asm__("dccci 0,%0": :"b"(addr));
  4005dc:	7c 00 4b 8c 	dccci   r0,r9
  4005e0:	39 29 00 20 	addi    r9,r9,32
  4005e4:	42 00 ff f8 	bdnz+   4005dc <embed_config+0x1c>
		}
	}

//	bd = &bdinfo;
//	*bdp = bd;
	bd->bi_memsize = XPAR_DDR_0_SIZE;
	bd->bi_intfreq = XPAR_CORE_CLOCK_FREQ_HZ;
	bd->bi_busfreq = XPAR_PLB_CLOCK_FREQ_HZ;
	bd->bi_pci_busfreq = XPAR_PCI_0_CLOCK_FREQ_HZ;
  4005e8:	38 00 00 00 	li      r0,0
  4005ec:	3d 20 04 00 	lis     r9,1024
  4005f0:	3d 60 11 e1 	lis     r11,4577
  4005f4:	3d 40 05 f5 	lis     r10,1525
	bd->bi_enetaddr[0] = bd->bi_enetaddr[0] = bd->bi_enetaddr[1] =
  4005f8:	98 03 00 04 	stb     r0,4(r3)
  4005fc:	91 23 00 00 	stw     r9,0(r3)
  400600:	90 03 00 14 	stw     r0,20(r3)
  400604:	98 03 00 09 	stb     r0,9(r3)
  400608:	98 03 00 08 	stb     r0,8(r3)
  40060c:	98 03 00 07 	stb     r0,7(r3)
  400610:	98 03 00 06 	stb     r0,6(r3)
  400614:	98 03 00 05 	stb     r0,5(r3)
  400618:	61 6b a3 00 	ori     r11,r11,41728
  40061c:	61 4a e1 00 	ori     r10,r10,57600
	  bd->bi_enetaddr[2] = bd->bi_enetaddr[3] = bd->bi_enetaddr[4] =
          bd->bi_enetaddr[5] = 0;
	timebase_period_ns = 1000000000 / bd->bi_tbfreq;
  400620:	38 00 00 03 	li      r0,3
  400624:	3d 20 00 40 	lis     r9,64
  400628:	91 63 00 0c 	stw     r11,12(r3)
  40062c:	91 43 00 10 	stw     r10,16(r3)
  400630:	90 09 40 5c 	stw     r0,16476(r9)
	/* see bi_tbfreq definition in arch/ppc/platforms/4xx/xilinx_ml300.h */
}
  400634:	4e 80 00 20 	blr