Attachment #74701 for bug #44121

Lines 1576-1582 static void evergreen_gpu_init(struct radeon_device *rdev) Link Here

(-)a/drivers/gpu/drm/radeon/evergreen.c (-1 / +17 lines)
1576	u32 sq_stack_resource_mgmt_3;	1576	u32 sq_stack_resource_mgmt_3;
1577	u32 vgt_cache_invalidation;	1577	u32 vgt_cache_invalidation;
1578	u32 hdp_host_path_cntl, tmp;	1578	u32 hdp_host_path_cntl, tmp;
1579	u32 disabled_rb_mask;	1579	u32 disabled_rb_mask, shader_pipe_config, rb_backend_disable;
1580	int i, j, num_shader_engines, ps_thread_count;	1580	int i, j, num_shader_engines, ps_thread_count;
1581		1581
1582	switch (rdev->family) {	1582	switch (rdev->family) {
Lines 1891-1899 static void evergreen_gpu_init(struct radeon_device *rdev) Link Here
1891	tmp \|= rb_disable_bitmap;	1891	tmp \|= rb_disable_bitmap;
1892	}	1892	}
1893	}	1893	}
		1894	WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES \| SE_BROADCAST_WRITES);
		1895	WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES \| SE_BROADCAST_WRITES);
1894	/* enabled rb are just the one not disabled :) */	1896	/* enabled rb are just the one not disabled :) */
1895	disabled_rb_mask = tmp;	1897	disabled_rb_mask = tmp;
1896		1898
		1899	rb_backend_disable = BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK << rdev->config.evergreen.max_backends) &
		1900	EVERGREEN_MAX_BACKENDS_MASK);
		1901	shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2;
		1902	shader_pipe_config \|= INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK << rdev->config.evergreen.max_pipes) &
		1903	EVERGREEN_MAX_PIPES_MASK);
		1904	shader_pipe_config \|= INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK << rdev->config.evergreen.max_simds) &
		1905	EVERGREEN_MAX_SIMDS_MASK);
		1906	for (i = 0; i < rdev->config.evergreen.num_ses; i++) {
		1907	WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES \| SE_INDEX(i));
		1908	WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES \| SE_INDEX(i));
		1909
		1910	WREG32(GC_USER_RB_BACKEND_DISABLE, rb_backend_disable);
		1911	WREG32(GC_USER_SHADER_PIPE_CONFIG, shader_pipe_config);
		1912	}
1897	WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES \| SE_BROADCAST_WRITES);	1913	WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES \| SE_BROADCAST_WRITES);
1898	WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES \| SE_BROADCAST_WRITES);	1914	WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES \| SE_BROADCAST_WRITES);
1899		1915

Lines 427-433 static void cayman_gpu_init(struct radeon_device *rdev) Link Here

(-)a/drivers/gpu/drm/radeon/ni.c (-1 / +18 lines)
427	u32 cgts_sm_ctrl_reg;	427	u32 cgts_sm_ctrl_reg;
428	u32 hdp_host_path_cntl;	428	u32 hdp_host_path_cntl;
429	u32 tmp;	429	u32 tmp;
430	u32 disabled_rb_mask;	430	u32 disabled_rb_mask, shader_pipe_config, rb_backend_disable;
431	int i, j;	431	int i, j;
432		432
433	switch (rdev->family) {	433	switch (rdev->family) {
Lines 594-602 static void cayman_gpu_init(struct radeon_device *rdev) Link Here
594	tmp <<= 4;	594	tmp <<= 4;
595	tmp \|= rb_disable_bitmap;	595	tmp \|= rb_disable_bitmap;
596	}	596	}
		597	WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES \| SE_BROADCAST_WRITES);
		598	WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES \| SE_BROADCAST_WRITES);
597	/* enabled rb are just the one not disabled :) */	599	/* enabled rb are just the one not disabled :) */
598	disabled_rb_mask = tmp;	600	disabled_rb_mask = tmp;
599		601
		602	rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE);
		603	rb_backend_disable \|= BACKEND_DISABLE((CAYMAN_MAX_BACKENDS_MASK << rdev->config.cayman.max_backends_per_se) &
		604	CAYMAN_MAX_BACKENDS_MASK);
		605	shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG);
		606	shader_pipe_config \|= INACTIVE_QD_PIPES((CAYMAN_MAX_PIPES_MASK << rdev->config.cayman.max_pipes_per_simd) &
		607	CAYMAN_MAX_PIPES_MASK);
		608	shader_pipe_config \|= INACTIVE_SIMDS((CAYMAN_MAX_SIMDS_MASK << rdev->config.cayman.max_simds_per_se) &
		609	CAYMAN_MAX_SIMDS_MASK);
		610	for (i = 0; i < rdev->config.cayman.num_shader_engines; i++) {
		611	WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES \| SE_INDEX(i));
		612	WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES \| SE_INDEX(i));
		613
		614	WREG32(GC_USER_RB_BACKEND_DISABLE, rb_backend_disable);
		615	WREG32(GC_USER_SHADER_PIPE_CONFIG, shader_pipe_config);
		616	}
600	WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES \| SE_BROADCAST_WRITES);	617	WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES \| SE_BROADCAST_WRITES);
601	WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES \| SE_BROADCAST_WRITES);	618	WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES \| SE_BROADCAST_WRITES);
602		619

Lines 1592-1597 void r600_gpu_init(struct radeon_device *rdev) Link Here

(-)a/drivers/gpu/drm/radeon/r600.c (+7 lines)
1592	tiling_config \|= tmp << 16;	1592	tiling_config \|= tmp << 16;
1593	rdev->config.r600.backend_map = tmp;	1593	rdev->config.r600.backend_map = tmp;
1594		1594
		1595	tmp = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
		1596	tmp \|= INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) &
		1597	R6XX_MAX_PIPES_MASK);
		1598	tmp \|= INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) &
		1599	R6XX_MAX_SIMDS_MASK);
		1600	WREG32(GC_USER_SHADER_PIPE_CONFIG, tmp);
		1601
1595	rdev->config.r600.tile_config = tiling_config;	1602	rdev->config.r600.tile_config = tiling_config;
1596	WREG32(GB_TILING_CONFIG, tiling_config);	1603	WREG32(GB_TILING_CONFIG, tiling_config);
1597	WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);	1604	WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);

Lines 555-560 static void rv770_gpu_init(struct radeon_device *rdev) Link Here

(-)a/drivers/gpu/drm/radeon/rv770.c (-1 / +7 lines)
555	gb_tiling_config \|= tmp << 16;	555	gb_tiling_config \|= tmp << 16;
556	rdev->config.rv770.backend_map = tmp;	556	rdev->config.rv770.backend_map = tmp;
557		557
		558	tmp = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
		559	tmp \|= INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) &
		560	R7XX_MAX_PIPES_MASK);
		561	tmp \|= INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) &
		562	R7XX_MAX_SIMDS_MASK);
		563	WREG32(GC_USER_SHADER_PIPE_CONFIG, tmp);
		564
558	if (rdev->family == CHIP_RV770)	565	if (rdev->family == CHIP_RV770)
559	gb_tiling_config \|= BANK_TILING(1);	566	gb_tiling_config \|= BANK_TILING(1);
560	else {	567	else {
561	-

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