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Lines 555-562
static u32 atombios_adjust_pll(struct drm_crtc *crtc,
Link Here
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| 555 |
dp_clock = dig_connector->dp_clock; |
555 |
dp_clock = dig_connector->dp_clock; |
| 556 |
} |
556 |
} |
| 557 |
} |
557 |
} |
| 558 |
/* this might work properly with the new pll algo */ |
558 |
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| 559 |
#if 0 /* doesn't work properly on some laptops */ |
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| 560 |
/* use recommended ref_div for ss */ |
559 |
/* use recommended ref_div for ss */ |
| 561 |
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
560 |
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
| 562 |
if (ss_enabled) { |
561 |
if (ss_enabled) { |
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Lines 566-583
static u32 atombios_adjust_pll(struct drm_crtc *crtc,
Link Here
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| 566 |
} |
565 |
} |
| 567 |
} |
566 |
} |
| 568 |
} |
567 |
} |
| 569 |
#endif |
568 |
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| 570 |
if (ASIC_IS_AVIVO(rdev)) { |
569 |
if (ASIC_IS_AVIVO(rdev)) { |
| 571 |
/* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ |
570 |
/* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ |
| 572 |
if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) |
571 |
if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) |
| 573 |
adjusted_clock = mode->clock * 2; |
572 |
adjusted_clock = mode->clock * 2; |
| 574 |
if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
573 |
if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
| 575 |
pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER; |
574 |
pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER; |
| 576 |
/* rv515 needs more testing with this option */ |
575 |
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
| 577 |
if (rdev->family != CHIP_RV515) { |
576 |
pll->flags |= RADEON_PLL_IS_LCD; |
| 578 |
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
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| 579 |
pll->flags |= RADEON_PLL_IS_LCD; |
| 580 |
} |
| 581 |
} else { |
577 |
} else { |
| 582 |
if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) |
578 |
if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) |
| 583 |
pll->flags |= RADEON_PLL_NO_ODD_POST_DIV; |
579 |
pll->flags |= RADEON_PLL_NO_ODD_POST_DIV; |
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Lines 957-967
static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
Link Here
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| 957 |
/* adjust pixel clock as needed */ |
953 |
/* adjust pixel clock as needed */ |
| 958 |
adjusted_clock = atombios_adjust_pll(crtc, mode, pll, ss_enabled, &ss); |
954 |
adjusted_clock = atombios_adjust_pll(crtc, mode, pll, ss_enabled, &ss); |
| 959 |
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955 |
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| 960 |
/* rv515 seems happier with the old algo */ |
956 |
if (ASIC_IS_AVIVO(rdev)) |
| 961 |
if (rdev->family == CHIP_RV515) |
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| 962 |
radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div, |
| 963 |
&ref_div, &post_div); |
| 964 |
else if (ASIC_IS_AVIVO(rdev)) |
| 965 |
radeon_compute_pll_avivo(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div, |
957 |
radeon_compute_pll_avivo(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div, |
| 966 |
&ref_div, &post_div); |
958 |
&ref_div, &post_div); |
| 967 |
else |
959 |
else |
| 968 |
- |
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