Attachment #4543 for bug #3022

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and this patch

Lines 273-278 Link Here

(-)linux-2.6.10-old/drivers/video/aty/radeon_base.c (+9 lines)
273	#ifdef CONFIG_MTRR	273	#ifdef CONFIG_MTRR
274	static int nomtrr = 0;	274	static int nomtrr = 0;
275	#endif	275	#endif
		276	#if defined(CONFIG_PM) && defined(CONFIG_X86)
		277	int radeon_force_sleep = 0;
		278	#endif
276		279
277	/*	280	/*
278	* prototypes	281	* prototypes
Lines 2532-2537 Link Here
2532	force_measure_pll = 1;	2535	force_measure_pll = 1;
2533	} else if (!strncmp(this_opt, "ignore_edid", 11)) {	2536	} else if (!strncmp(this_opt, "ignore_edid", 11)) {
2534	ignore_edid = 1;	2537	ignore_edid = 1;
		2538	#if defined(CONFIG_PM) && defined(CONFIG_X86)
		2539	} else if (!strncmp(this_opt, "force_sleep", 11)) {
		2540	radeon_force_sleep = 1;
		2541	#endif
2535	} else	2542	} else
2536	mode_option = this_opt;	2543	mode_option = this_opt;
2537	}	2544	}
Lines 2571-2573 Link Here
2571	MODULE_PARM_DESC(panel_yres, "int: set panel yres");	2578	MODULE_PARM_DESC(panel_yres, "int: set panel yres");
2572	module_param(mode_option, charp, 0);	2579	module_param(mode_option, charp, 0);
2573	MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");	2580	MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
		2581	module_param(radeon_force_sleep, int, 0);
		2582	MODULE_PARM_DESC(radeon_force_sleep, "bool: force ACPI sleep mode on untested machines");





/*
 *	drivers/video/aty/radeon_base.c
 *
 *	framebuffer driver for ATI Radeon chipset video boards
 *
 *	Copyright 2003	Ben. Herrenschmidt <benh@kernel.crashing.org>


#ifdef CONFIG_PPC_OF

#include <asm/prom.h>
#include <asm/pci-bridge.h>
#include "../macmodes.h"


	CHIP_DEF(PCI_CHIP_RV250_Ig,	RV250,	CHIP_HAS_CRTC2),
	/* Mobility 9100 IGP (U3) */
	CHIP_DEF(PCI_CHIP_RS300_5835,	RS300,	CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
	CHIP_DEF(PCI_CHIP_RS350_7835,	RS300,	CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
	/* 9100 IGP (A5) */
	CHIP_DEF(PCI_CHIP_RS300_5834,	RS300,	CHIP_HAS_CRTC2 | CHIP_IS_IGP),
	CHIP_DEF(PCI_CHIP_RS350_7834,	RS300,	CHIP_HAS_CRTC2 | CHIP_IS_IGP),
	/* Mobility 9200 (M9+) */
	CHIP_DEF(PCI_CHIP_RV280_5C61,	RV280,	CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
	CHIP_DEF(PCI_CHIP_RV280_5C63,	RV280,	CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),

	CHIP_DEF(PCI_CHIP_R350_NI,	R350,	CHIP_HAS_CRTC2),
	CHIP_DEF(PCI_CHIP_R360_NJ,	R350,	CHIP_HAS_CRTC2),
	CHIP_DEF(PCI_CHIP_R350_NK,	R350,	CHIP_HAS_CRTC2),
	/* Newer stuff */
	CHIP_DEF(PCI_CHIP_RV380_3E50,	RV380,	CHIP_HAS_CRTC2),
	CHIP_DEF(PCI_CHIP_RV380_3E54,	RV380,	CHIP_HAS_CRTC2),
	CHIP_DEF(PCI_CHIP_RV380_3150,	RV380,	CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
	CHIP_DEF(PCI_CHIP_RV380_3154,	RV380,	CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
	CHIP_DEF(PCI_CHIP_RV370_5B60,	RV380,	CHIP_HAS_CRTC2),
	CHIP_DEF(PCI_CHIP_RV370_5B62,	RV380,	CHIP_HAS_CRTC2),
	CHIP_DEF(PCI_CHIP_RV370_5B64,	RV380,	CHIP_HAS_CRTC2),
	CHIP_DEF(PCI_CHIP_RV370_5B65,	RV380,	CHIP_HAS_CRTC2),
	CHIP_DEF(PCI_CHIP_RV370_5460,	RV380,	CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
	CHIP_DEF(PCI_CHIP_RV370_5464,	RV380,	CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
	CHIP_DEF(PCI_CHIP_R420_JH,	R420,	CHIP_HAS_CRTC2),
	CHIP_DEF(PCI_CHIP_R420_JI,	R420,	CHIP_HAS_CRTC2),
	CHIP_DEF(PCI_CHIP_R420_JJ,	R420,	CHIP_HAS_CRTC2),
	CHIP_DEF(PCI_CHIP_R420_JK,	R420,	CHIP_HAS_CRTC2),
	CHIP_DEF(PCI_CHIP_R420_JL,	R420,	CHIP_HAS_CRTC2),
	CHIP_DEF(PCI_CHIP_R420_JM,	R420,	CHIP_HAS_CRTC2),
	CHIP_DEF(PCI_CHIP_R420_JN,	R420,	CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
	CHIP_DEF(PCI_CHIP_R420_JP,	R420,	CHIP_HAS_CRTC2),
	CHIP_DEF(PCI_CHIP_R423_UH,	R420,	CHIP_HAS_CRTC2),
	CHIP_DEF(PCI_CHIP_R423_UI,	R420,	CHIP_HAS_CRTC2),
	CHIP_DEF(PCI_CHIP_R423_UJ,	R420,	CHIP_HAS_CRTC2),
	CHIP_DEF(PCI_CHIP_R423_UK,	R420,	CHIP_HAS_CRTC2),
	CHIP_DEF(PCI_CHIP_R423_UQ,	R420,	CHIP_HAS_CRTC2),
	CHIP_DEF(PCI_CHIP_R423_UR,	R420,	CHIP_HAS_CRTC2),
	CHIP_DEF(PCI_CHIP_R423_UT,	R420,	CHIP_HAS_CRTC2),
	CHIP_DEF(PCI_CHIP_R423_5D57,	R420,	CHIP_HAS_CRTC2),
	/* Original Radeon/7200 */
	CHIP_DEF(PCI_CHIP_RADEON_QD,	RADEON,	0),
	CHIP_DEF(PCI_CHIP_RADEON_QE,	RADEON,	0),

static char *mode_option;
static char *monitor_layout;
static int noaccel = 0;
static int default_dynclk = -2;
static int nomodeset = 0;
static int ignore_edid = 0;
static int mirror = 0;

                                                                                                          
	rom = pci_map_rom(dev, &rom_size);
	if (!rom) {
		printk(KERN_ERR "radeonfb (%s): ROM failed to map\n",
		       pci_name(rinfo->pdev));
		return -ENOMEM;
	}
	


	/* Very simple test to make sure it appeared */
	if (BIOS_IN16(0) != 0xaa55) {
		printk(KERN_ERR "radeonfb (%s): Invalid ROM signature %x should be"
		       "0xaa55\n", pci_name(rinfo->pdev), BIOS_IN16(0));
		goto failed;
	}
	/* Look for the PCI data to check the ROM type */

	 * } pci_data_t;
	 */
	if (BIOS_IN32(dptr) !=  (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
		printk(KERN_WARNING "radeonfb (%s): PCI DATA signature in ROM"
		       "incorrect: %08x\n", pci_name(rinfo->pdev), BIOS_IN32(dptr));
		goto anyway;
	}
	rom_type = BIOS_IN8(dptr + 0x14);

 */
static int __devinit radeon_read_xtal_OF (struct radeonfb_info *rinfo)
{
	struct device_node *dp = rinfo->of_node;
	u32 *val;

	if (dp == NULL)
	if (dp == NULL) {
		printk(KERN_WARNING "radeonfb: Cannot match card to OF node !\n");
		return -ENODEV;
	}
	val = (u32 *) get_property(dp, "ATY,RefCLK", NULL);
	if (!val || !*val) {
		printk(KERN_WARNING "radeonfb: No ATY,RefCLK property !\n");

		denom = 1;
		break;
	case 1:
		n = ((INPLL(M_SPLL_REF_FB_DIV) >> 16) & 0xff);
		m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
		num = 2*n;
		denom = 2*m;
		break;
	case 2:
		n = ((INPLL(M_SPLL_REF_FB_DIV) >> 8) & 0xff);
		m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
		num = 2*n;
		denom = 2*m;
        break;
	}

	ppll_div_sel = INREG8(CLOCK_CNTL_INDEX + 1) & 0x3;

	n = (INPLL(PPLL_DIV_0 + ppll_div_sel) & 0x7ff);
	m = (INPLL(PPLL_REF_DIV) & 0x3ff);

		return -1;
	}

	tmp = INPLL(M_SPLL_REF_FB_DIV);
	ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;

	Ns = (tmp & 0xff0000) >> 16;

		rinfo->pll.ref_clk = 2700;
		break;
	}
	rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;


#ifdef CONFIG_PPC_OF

}


int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch)
{
        u32 val;
	u32 tmp_pix_clks;
	int unblank = 0;

	if (rinfo->lock_blank)
		return 0;

        val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
                 CRTC_VSYNC_DIS);
        switch (blank) {
	case FB_BLANK_UNBLANK:
	case FB_BLANK_NORMAL:
		break;
	case FB_BLANK_VSYNC_SUSPEND:
		val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS);
		break;

		val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS |
			CRTC_HSYNC_DIS);
		break;
	case FB_BLANK_NORMAL:
		val |= CRTC_DISPLAY_DIS;
		break;
	case FB_BLANK_UNBLANK:
	default:
		unblank = 1;
        }
	OUTREG(CRTC_EXT_CNTL, val);


	switch (rinfo->mon1_type) {
	case MT_DFP:
		if (unblank)
			break;
		if (blank == FB_BLANK_UNBLANK ||
		    blank == FB_BLANK_NORMAL)
			OUTREGP(FP_GEN_CNTL, (FP_FPON | FP_TMDS_EN),
				~(FP_FPON | FP_TMDS_EN));
		else {
			if (mode_switch || blank == FB_BLANK_NORMAL)
				break;
			OUTREGP(FP_GEN_CNTL, 0, ~(FP_FPON | FP_TMDS_EN));
		}
		break;
	case MT_LCD:
		del_timer_sync(&rinfo->lvds_timer);
		val = INREG(LVDS_GEN_CNTL);
		if (unblank) {
		    blank == FB_BLANK_NORMAL) {
			u32 target_val = (val & ~LVDS_DISPLAY_DIS) | LVDS_BLON | LVDS_ON
				| LVDS_EN | (rinfo->init_state.lvds_gen_cntl
					     & (LVDS_DIGON | LVDS_BL_MOD_EN));
			if ((val ^ target_val) == LVDS_DISPLAY_DIS)
				OUTREG(LVDS_GEN_CNTL, target_val);
			else if ((val ^ target_val) != 0) {
				OUTREG(LVDS_GEN_CNTL, target_val
				       & ~(LVDS_ON | LVDS_BL_MOD_EN));
				rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
				rinfo->init_state.lvds_gen_cntl |=
					target_val & LVDS_STATE_MASK;
				if (mode_switch) {
					radeon_msleep(rinfo->panel_info.pwr_delay);
					OUTREG(LVDS_GEN_CNTL, target_val);
				}
				else {
					rinfo->pending_lvds_gen_cntl = target_val;
					mod_timer(&rinfo->lvds_timer,
					   jiffies +
					   msecs_to_jiffies(rinfo->panel_info.pwr_delay));
				}
			}
		} else {

			OUTREG(LVDS_GEN_CNTL, val);

			/* We don't do a full switch-off on a simple mode switch */
			if (mode_switch || blank == FB_BLANK_NORMAL)
				break;

			/* Asic bug, when turning off LVDS_ON, we have to make sure

			tmp_pix_clks = INPLL(PIXCLKS_CNTL);
			if (rinfo->is_mobility || rinfo->is_IGP)
				OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb);
			val &= ~(LVDS_BL_MOD_EN);
			OUTREG(LVDS_GEN_CNTL, val);
			udelay(100);
			val &= ~(LVDS_ON | LVDS_EN);
			OUTREG(LVDS_GEN_CNTL, val);
			val &= ~LVDS_DIGON;
			rinfo->pending_lvds_gen_cntl = val;
			mod_timer(&rinfo->lvds_timer,
				  jiffies +
				  msecs_to_jiffies(rinfo->panel_info.pwr_delay));
			rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
			rinfo->init_state.lvds_gen_cntl |= val & LVDS_STATE_MASK;
			if (rinfo->is_mobility || rinfo->is_IGP)

	return (blank == FB_BLANK_NORMAL) ? -EINVAL : 0;
}

static int radeonfb_blank (int blank, struct fb_info *info)
{
        struct radeonfb_info *rinfo = info->par;

	if (rinfo->asleep)
		return 0;
		
	return radeon_screen_blank(rinfo, blank, 0);

	return 0;
}

static int radeonfb_setcolreg (unsigned regno, unsigned red, unsigned green,

}


void radeon_save_state (struct radeonfb_info *rinfo, struct radeon_regs *save)
{
	/* CRTC regs */
	save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);

	save->fp_vert_stretch = INREG(FP_VERT_STRETCH);
	save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
	save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL);
	save->tmds_crc = INREG(TMDS_CRC);
	save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL);
	save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL);

	/* PLL regs */
	save->clk_cntl_index = INREG(CLOCK_CNTL_INDEX) & ~0x3f;
	save->ppll_div_3 = INPLL(PPLL_DIV_3);
	save->ppll_ref_div = INPLL(PPLL_REF_DIV);
}




	/* Workaround from XFree */
	if (rinfo->is_mobility) {
	        /* A temporal workaround for the occational blanking on certain laptop
		 * panels. This appears to related to the PLL divider registers
		 * (fail to lock?). It occurs even when all dividers are the same
		 * with their old settings. In this case we really don't need to
		 * fiddle with PLL registers. By doing this we can avoid the blanking
		 * problem with some panels.
	         */
		if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) &&
		    (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) &
					  (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) {
			/* We still have to force a switch to selected PPLL div thanks to
			 * an XFree86 driver bug which will switch it away in some cases
			 * even when using UseFDev */
			OUTREGP(CLOCK_CNTL_INDEX,
				mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
				~PPLL_DIV_SEL_MASK);
            		return;
		}
	}

		PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN,
		~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));

	/* Switch to selected PPLL divider */
	OUTREGP(CLOCK_CNTL_INDEX,
		mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
		~PPLL_DIV_SEL_MASK);

	/* Set PPLL ref. div */
	if (rinfo->family == CHIP_FAMILY_R300 ||

		~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));

	/* We may want some locking ... oh well */
       	radeon_msleep(5);

	/* Switch back VCLK source to PPLL */
	OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK);

{
	struct radeonfb_info *rinfo = (struct radeonfb_info *)data;

	radeon_engine_idle();

	OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl);
	if (rinfo->pending_pixclks_cntl) {
		OUTPLL(PIXCLKS_CNTL, rinfo->pending_pixclks_cntl);
		rinfo->pending_pixclks_cntl = 0;
	}
}

/*
 * Apply a video mode. This will apply the whole register set, including
 * the PLL registers, to the card
 */
void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
			int regs_only)
{
	int i;
	int primary_mon = PRIMARY_MONITOR(rinfo);

	if (nomodeset)
		return;

	if (!regs_only)
		radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0);
	radeon_screen_blank(rinfo, FB_BLANK_POWERDOWN, 1);
	msleep(100);

	radeon_fifo_wait(31);
	for (i=0; i<10; i++)

		OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl);
	}

	if (!regs_only)
		radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0);

	radeon_fifo_wait(2);
	OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);

	       rinfo->pll.ref_div, rinfo->pll.ref_clk,
	       pll_output_freq);

	/* If we fall through the bottom, try the "default value"
	   given by the terminal post_div->bitvalue */
	if ( !post_div->divider ) {
		post_div = &post_divs[post_div->bitvalue];
		pll_output_freq = post_div->divider * freq;
	}
	RTRACE("ref_div = %d, ref_clk = %d, output_freq = %d\n",
	       rinfo->pll.ref_div, rinfo->pll.ref_clk,
	       pll_output_freq);

	fb_div = round_div(rinfo->pll.ref_div*pll_output_freq,
				  rinfo->pll.ref_clk);
	regs->ppll_ref_div = rinfo->pll.ref_div;

	RTRACE("ppll_div_3 = 0x%x\n", regs->ppll_div_3);
}

static int radeonfb_set_par(struct fb_info *info)
{
	struct radeonfb_info *rinfo = info->par;
	struct fb_var_screeninfo *mode = &info->var;
	struct radeon_regs *newmode;
	int hTotal, vTotal, hSyncStart, hSyncEnd,
	    hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync;
	u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};
	u8 hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5};
	u32 sync, h_sync_pol, v_sync_pol, dotClock, pixClock;
	int i, freq;
	int format = 0;
	int nopllcalc = 0;
	int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid;
	int primary_mon = PRIMARY_MONITOR(rinfo);
	int depth = var_to_depth(mode);
	int use_rmx = 0;

	newmode = kmalloc(sizeof(struct radeon_regs), GFP_KERNEL);
	if (!newmode)
		return -ENOMEM;

	/* We always want engine to be idle on a mode switch, even
	 * if we won't actually change the mode


		if (rinfo->panel_info.use_bios_dividers) {
			nopllcalc = 1;
			newmode->ppll_div_3 = rinfo->panel_info.fbk_divider |
				(rinfo->panel_info.post_divider << 16);
			newmode->ppll_ref_div = rinfo->panel_info.ref_divider;
		}
	}
	dotClock = 1000000000 / pixClock;


	hsync_start = hSyncStart - 8 + hsync_fudge;

	newmode->crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN |
				(format << 8);

	/* Clear auto-center etc... */
	newmode->crtc_more_cntl = rinfo->init_state.crtc_more_cntl;
	newmode->crtc_more_cntl &= 0xfffffff0;
	
	if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
		newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;
		if (mirror)
			newmode->crtc_ext_cntl |= CRTC_CRT_ON;

		newmode->crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN |
					   CRTC_INTERLACE_EN);
	} else {
		newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN |
					CRTC_CRT_ON;
	}

	newmode->dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN |
			   DAC_8BIT_EN;

	newmode->crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) |
				     (((mode->xres / 8) - 1) << 16));

	newmode->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
					(hsync_wid << 16) | (h_sync_pol << 23));

	newmode->crtc_v_total_disp = ((vTotal - 1) & 0xffff) |
				    ((mode->yres - 1) << 16);

	newmode->crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) |
					 (vsync_wid << 16) | (v_sync_pol  << 23));

	if (!(info->flags & FBINFO_HWACCEL_DISABLED)) {

 				& ~(0x3f)) >> 6;

		/* Then, re-multiply it to get the CRTC pitch */
		newmode->crtc_pitch = (rinfo->pitch << 3) / ((mode->bits_per_pixel + 1) / 8);
	} else
		newmode->crtc_pitch = (mode->xres_virtual >> 3);

	newmode->crtc_pitch |= (newmode->crtc_pitch << 16);

	/*
	 * It looks like recent chips have a problem with SURFACE_CNTL,
	 * setting SURF_TRANSLATION_DIS completely disables the
	 * swapper as well, so we leave it unset now.
	 */
	newmode->surface_cntl = 0;

#if defined(__BIG_ENDIAN)


	 */
	switch (mode->bits_per_pixel) {
		case 16:
			newmode->surface_cntl |= NONSURF_AP0_SWP_16BPP;
			newmode->surface_cntl |= NONSURF_AP1_SWP_16BPP;
			break;
		case 24:	
		case 32:
			newmode->surface_cntl |= NONSURF_AP0_SWP_32BPP;
			newmode->surface_cntl |= NONSURF_AP1_SWP_32BPP;
			break;
	}
#endif

	/* Clear surface registers */
	for (i=0; i<8; i++) {
		newmode->surf_lower_bound[i] = 0;
		newmode->surf_upper_bound[i] = 0x1f;
		newmode->surf_info[i] = 0;
	}

	RTRACE("h_total_disp = 0x%x\t   hsync_strt_wid = 0x%x\n",
		newmode->crtc_h_total_disp, newmode->crtc_h_sync_strt_wid);
	RTRACE("v_total_disp = 0x%x\t   vsync_strt_wid = 0x%x\n",
		newmode->crtc_v_total_disp, newmode->crtc_v_sync_strt_wid);

	rinfo->bpp = mode->bits_per_pixel;
	rinfo->depth = depth;

	RTRACE("pixclock = %lu\n", (unsigned long)pixClock);
	RTRACE("freq = %lu\n", (unsigned long)freq);

	/* We use PPLL_DIV_3 */
	newmode->clk_cntl_index = 0x300;

	/* Calculate PPLL value if necessary */
	if (!nopllcalc)
		radeon_calc_pll_regs(rinfo, newmode, freq);

	newmode->vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl;

	if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
		unsigned int hRatio, vRatio;

		if (mode->yres > rinfo->panel_info.yres)
			mode->yres = rinfo->panel_info.yres;

		newmode->fp_horz_stretch = (((rinfo->panel_info.xres / 8) - 1)
					   << HORZ_PANEL_SHIFT);
		newmode->fp_vert_stretch = ((rinfo->panel_info.yres - 1)
					   << VERT_PANEL_SHIFT);

		if (mode->xres != rinfo->panel_info.xres) {
			hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX,
					   rinfo->panel_info.xres);
			newmode->fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) |
						   (newmode->fp_horz_stretch &
						    (HORZ_PANEL_SIZE | HORZ_FP_LOOP_STRETCH |
						     HORZ_AUTO_RATIO_INC)));
			newmode->fp_horz_stretch |= (HORZ_STRETCH_BLEND |
						    HORZ_STRETCH_ENABLE);
			use_rmx = 1;
		}
		newmode->fp_horz_stretch &= ~HORZ_AUTO_RATIO;

		if (mode->yres != rinfo->panel_info.yres) {
			vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX,
					   rinfo->panel_info.yres);
			newmode->fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) |
						   (newmode->fp_vert_stretch &
						   (VERT_PANEL_SIZE | VERT_STRETCH_RESERVED)));
			newmode->fp_vert_stretch |= (VERT_STRETCH_BLEND |
						    VERT_STRETCH_ENABLE);
			use_rmx = 1;
		}
		newmode->fp_vert_stretch &= ~VERT_AUTO_RATIO_EN;

		newmode->fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32)
				       ~(FP_SEL_CRTC2 |
					 FP_RMX_HVSYNC_CONTROL_EN |
					 FP_DFP_SYNC_SEL |

					 FP_CRTC_USE_SHADOW_VEND |
					 FP_CRT_SYNC_ALT));

		newmode->fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR |
					FP_CRTC_DONT_SHADOW_HEND |
					FP_PANEL_FORMAT);

		if (IS_R300_VARIANT(rinfo) ||
		    (rinfo->family == CHIP_FAMILY_R200)) {
			newmode->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
			if (use_rmx)
				newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
			else
				newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
		} else
			newmode->fp_gen_cntl |= FP_SEL_CRTC1;

		newmode->lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl;
		newmode->lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl;
		newmode->tmds_crc = rinfo->init_state.tmds_crc;
		newmode->tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl;

		if (primary_mon == MT_LCD) {
			newmode->lvds_gen_cntl |= (LVDS_ON | LVDS_BLON);
			newmode->fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN);
		} else {
			/* DFP */
			newmode->fp_gen_cntl |= (FP_FPON | FP_TMDS_EN);
			newmode->tmds_transmitter_cntl = (TMDS_RAN_PAT_RST | TMDS_ICHCSEL) &
							 ~(TMDS_PLLRST);
			/* TMDS_PLL_EN bit is reversed on RV (and mobility) chips */
			if (IS_R300_VARIANT(rinfo) ||
			    (rinfo->family == CHIP_FAMILY_R350) ||
			    (rinfo->family == CHIP_FAMILY_RV350) ||
			    (rinfo->family == CHIP_FAMILY_R200) || !rinfo->has_CRTC2)
				newmode->tmds_transmitter_cntl &= ~TMDS_PLL_EN;
			else
				newmode->tmds_transmitter_cntl |= TMDS_PLL_EN;
			newmode->crtc_ext_cntl &= ~CRTC_CRT_ON;
		}

		newmode->fp_crtc_h_total_disp = (((rinfo->panel_info.hblank / 8) & 0x3ff) |
				(((mode->xres / 8) - 1) << 16));
		newmode->fp_crtc_v_total_disp = (rinfo->panel_info.vblank & 0xffff) |
				((mode->yres - 1) << 16);
		newmode->fp_h_sync_strt_wid = ((rinfo->panel_info.hOver_plus & 0x1fff) |
				(hsync_wid << 16) | (h_sync_pol << 23));
		newmode->fp_v_sync_strt_wid = ((rinfo->panel_info.vOver_plus & 0xfff) |
				(vsync_wid << 16) | (v_sync_pol  << 23));
	}

	/* do it! */
	if (!rinfo->asleep) {
		memcpy(&rinfo->state, newmode, sizeof(*newmode));
		radeon_write_mode (rinfo, newmode, 0);
		/* (re)initialize the engine */
		if (!(info->flags & FBINFO_HWACCEL_DISABLED))
			radeonfb_engine_init (rinfo);

			     rinfo->depth, info->fix.line_length);
#endif

	kfree(newmode);
	return 0;
}


	if (on && (level > BACKLIGHT_OFF)) {
		lvds_gen_cntl &= ~LVDS_DISPLAY_DIS;
		if (!(lvds_gen_cntl & LVDS_BLON) || !(lvds_gen_cntl & LVDS_ON)) {
			lvds_gen_cntl |= (rinfo->init_state.lvds_gen_cntl & LVDS_DIGON);
			lvds_gen_cntl |= LVDS_BLON | LVDS_EN;
			OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
			lvds_gen_cntl &= ~LVDS_BL_MOD_LEVEL_MASK;
			lvds_gen_cntl |= (conv_table[level] <<
					  LVDS_BL_MOD_LEVEL_SHIFT);
			lvds_gen_cntl |= LVDS_ON;
			lvds_gen_cntl |= (rinfo->init_state.lvds_gen_cntl & LVDS_BL_MOD_EN);
			rinfo->pending_lvds_gen_cntl = lvds_gen_cntl;
			mod_timer(&rinfo->lvds_timer,
				  jiffies + msecs_to_jiffies(rinfo->panel_info.pwr_delay));

		tmpPixclksCntl = INPLL(PIXCLKS_CNTL);
		if (rinfo->is_mobility || rinfo->is_IGP)
			OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb);
		lvds_gen_cntl &= ~(LVDS_BL_MOD_LEVEL_MASK | LVDS_BL_MOD_EN);
		lvds_gen_cntl |= (conv_table[0] <<
				  LVDS_BL_MOD_LEVEL_SHIFT);
		lvds_gen_cntl |= LVDS_DISPLAY_DIS;
		OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
		udelay(100);
		lvds_gen_cntl &= ~(LVDS_ON | LVDS_EN);
		OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
		lvds_gen_cntl &= ~(LVDS_DIGON);
		rinfo->pending_lvds_gen_cntl = lvds_gen_cntl;
		mod_timer(&rinfo->lvds_timer,
			  jiffies + msecs_to_jiffies(rinfo->panel_info.pwr_delay));
		if (rinfo->is_mobility || rinfo->is_IGP)
			OUTPLL(PIXCLKS_CNTL, tmpPixclksCntl);
	}

 * local (0xe0000000 for now) that will be changed by XFree/DRI anyway
 */
#ifdef CONFIG_PPC_OF
#define SET_MC_FB_FROM_APERTURE
static void fixup_memory_mappings(struct radeonfb_info *rinfo)
{
	u32 save_crtc_gen_cntl, save_crtc2_gen_cntl = 0;

	OUTREG(DISPLAY_BASE_ADDR, aper_base);
	if (rinfo->has_CRTC2)
		OUTREG(CRTC2_DISPLAY_BASE_ADDR, aper_base);
	OUTREG(OV0_BASE_ADDR, aper_base);
#else
	OUTREG(DISPLAY_BASE_ADDR, 0);
	if (rinfo->has_CRTC2)
		OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0);
	OUTREG(OV0_BASE_ADDR, 0);
#endif
	mdelay(100);


#endif /* CONFIG_PPC_OF */


static void radeon_identify_vram(struct radeonfb_info *rinfo)
{
	u32 tmp;

	/* framebuffer size */
        if ((rinfo->family == CHIP_FAMILY_RS100) ||
            (rinfo->family == CHIP_FAMILY_RS200) ||
            (rinfo->family == CHIP_FAMILY_RS300)) {
          u32 tom = INREG(NB_TOM);
          tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024);

 		radeon_fifo_wait(6);
          OUTREG(MC_FB_LOCATION, tom);
          OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
          OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
          OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16);

          /* This is supposed to fix the crtc2 noise problem. */
          OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000);

          if ((rinfo->family == CHIP_FAMILY_RS100) ||
              (rinfo->family == CHIP_FAMILY_RS200)) {
             /* This is to workaround the asic bug for RMX, some versions
                of BIOS dosen't have this register initialized correctly.
             */
             OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN,
                     ~CRTC_H_CUTOFF_ACTIVE_EN);
          }
        } else {
          tmp = INREG(CONFIG_MEMSIZE);
        }

	/* mem size is bits [28:0], mask off the rest */
	rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;

	/*
	 * Hack to get around some busted production M6's
	 * reporting no ram
	 */
	if (rinfo->video_ram == 0) {
		switch (rinfo->pdev->device) {
	       	case PCI_CHIP_RADEON_LY:
		case PCI_CHIP_RADEON_LZ:
	       		rinfo->video_ram = 8192 * 1024;
	       		break;
	       	default:
	       		break;
		}
	}


	/*
	 * Now try to identify VRAM type
	 */
	if (rinfo->is_IGP || (rinfo->family >= CHIP_FAMILY_R300) ||
	    (INREG(MEM_SDRAM_MODE_REG) & (1<<30)))
		rinfo->vram_ddr = 1;
	else
		rinfo->vram_ddr = 0;

	tmp = INREG(MEM_CNTL);
	if (IS_R300_VARIANT(rinfo)) {
		tmp &=  R300_MEM_NUM_CHANNELS_MASK;
		switch (tmp) {
		case 0:  rinfo->vram_width = 64; break;
		case 1:  rinfo->vram_width = 128; break;
		case 2:  rinfo->vram_width = 256; break;
		default: rinfo->vram_width = 128; break;
		}
	} else if ((rinfo->family == CHIP_FAMILY_RV100) ||
		   (rinfo->family == CHIP_FAMILY_RS100) ||
		   (rinfo->family == CHIP_FAMILY_RS200)){
		if (tmp & RV100_MEM_HALF_MODE)
			rinfo->vram_width = 32;
		else
			rinfo->vram_width = 64;
	} else {
		if (tmp & MEM_NUM_CHANNELS_MASK)
			rinfo->vram_width = 128;
		else
			rinfo->vram_width = 64;
	}

	/* This may not be correct, as some cards can have half of channel disabled
	 * ToDo: identify these cases
	 */

	RTRACE("radeonfb (%s): Found %ldk of %s %d bits wide videoram\n",
	       pci_name(rinfo->pdev),
	       rinfo->video_ram / 1024,
	       rinfo->vram_ddr ? "DDR" : "SDRAM",
	       rinfo->vram_width);
}

/*
 * Sysfs
 */

{
	struct fb_info *info;
	struct radeonfb_info *rinfo;
	u32 tmp;
	int ret;

	RTRACE("radeonfb_pci_register BEGIN\n");

	/* Enable device in PCI config */
	ret = pci_enable_device(pdev);
	if (ret < 0) {
		printk(KERN_ERR "radeonfb (%s): Cannot enable PCI device\n",
		       pci_name(pdev));
		goto err_out;
	}

	info = framebuffer_alloc(sizeof(struct radeonfb_info), &pdev->dev);
	if (!info) {
		printk (KERN_ERR "radeonfb (%s): could not allocate memory\n",
			pci_name(pdev));
		ret = -ENOMEM;
		goto err_disable;
	}

	/* request the mem regions */
	ret = pci_request_regions(pdev, "radeonfb");
	if (ret < 0) {
		printk( KERN_ERR "radeonfb (%s): cannot reserve PCI regions."
			"  Someone already got them?\n", pci_name(rinfo->pdev));
		goto err_release_fb;
	}

	/* map the regions */
	rinfo->mmio_base = ioremap(rinfo->mmio_base_phys, RADEON_REGSIZE);
	if (!rinfo->mmio_base) {
		printk(KERN_ERR "radeonfb (%s): cannot map MMIO\n", pci_name(rinfo->pdev));
		ret = -EIO;
		goto err_release_pci;
	}

	rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;

#ifdef CONFIG_PPC_OF
	/* On PPC, we obtain the OF device-node pointer to the firmware
	 * data for this chip
	 */
	rinfo->of_node = pci_device_to_OF_node(pdev);
	if (rinfo->of_node == NULL)
		printk(KERN_WARNING "radeonfb (%s): Cannot match card to OF node !\n",
		       pci_name(rinfo->pdev));

	/* On PPC, the firmware sets up a memory mapping that tends
	 * to cause lockups when enabling the engine. We reconfigure
	 * the card internal memory mappings properly
	 */
#ifdef CONFIG_PPC_OF
	fixup_memory_mappings(rinfo);
#else	
	rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
#endif /* CONFIG_PPC_OF */

	/* Get VRAM size and type */
	radeon_identify_vram(rinfo);
            (rinfo->family == CHIP_FAMILY_RS200) ||
            (rinfo->family == CHIP_FAMILY_RS300)) {
          u32 tom = INREG(NB_TOM);
          tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024);
 
 		radeon_fifo_wait(6);
          OUTREG(MC_FB_LOCATION, tom);
          OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
          OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
          OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16);
 
          /* This is supposed to fix the crtc2 noise problem. */
          OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000);
 
          if ((rinfo->family == CHIP_FAMILY_RS100) ||
              (rinfo->family == CHIP_FAMILY_RS200)) {
             /* This is to workaround the asic bug for RMX, some versions
                of BIOS dosen't have this register initialized correctly.
             */
             OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN,
                     ~CRTC_H_CUTOFF_ACTIVE_EN);
          }
        } else {
          tmp = INREG(CONFIG_MEMSIZE);
        }

	/* mem size is bits [28:0], mask off the rest */
	rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;

	/* ram type */
	tmp = INREG(MEM_SDRAM_MODE_REG);
	switch ((MEM_CFG_TYPE & tmp) >> 30) {
       	case 0:
       		/* SDR SGRAM (2:1) */
       		strcpy(rinfo->ram_type, "SDR SGRAM");
       		rinfo->ram.ml = 4;
       		rinfo->ram.mb = 4;
       		rinfo->ram.trcd = 1;
       		rinfo->ram.trp = 2;
       		rinfo->ram.twr = 1;
       		rinfo->ram.cl = 2;
       		rinfo->ram.loop_latency = 16;
       		rinfo->ram.rloop = 16;
       		break;
       	case 1:
       		/* DDR SGRAM */
       		strcpy(rinfo->ram_type, "DDR SGRAM");
       		rinfo->ram.ml = 4;
       		rinfo->ram.mb = 4;
       		rinfo->ram.trcd = 3;
       		rinfo->ram.trp = 3;
       		rinfo->ram.twr = 2;
       		rinfo->ram.cl = 3;
       		rinfo->ram.tr2w = 1;
       		rinfo->ram.loop_latency = 16;
       		rinfo->ram.rloop = 16;
		break;
       	default:
       		/* 64-bit SDR SGRAM */
       		strcpy(rinfo->ram_type, "SDR SGRAM 64");
       		rinfo->ram.ml = 4;
       		rinfo->ram.mb = 8;
       		rinfo->ram.trcd = 3;
       		rinfo->ram.trp = 3;
       		rinfo->ram.twr = 1;
       		rinfo->ram.cl = 3;
       		rinfo->ram.tr2w = 1;
       		rinfo->ram.loop_latency = 17;
       		rinfo->ram.rloop = 17;
		break;
	}

	/*
	 * Hack to get around some busted production M6's
	 * reporting no ram
	 */
	if (rinfo->video_ram == 0) {
		switch (pdev->device) {
	       	case PCI_CHIP_RADEON_LY:
		case PCI_CHIP_RADEON_LZ:
	       		rinfo->video_ram = 8192 * 1024;
	       		break;
	       	default:
			printk (KERN_ERR "radeonfb: no video RAM reported\n");
			ret = -ENXIO;
			goto err_unmap_rom;
		}
	}

	RTRACE("radeonfb: probed %s %ldk videoram\n", (rinfo->ram_type), (rinfo->video_ram/1024));

	rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, rinfo->video_ram);


	if (rinfo->fb_base)
		memset_io(rinfo->fb_base, 0, rinfo->mapped_vram);
	else {
		printk (KERN_ERR "radeonfb (%s): cannot map FB\n", pci_name(rinfo->pdev));
		ret = -EIO;
		goto err_unmap_rom;
	}

	RTRACE("radeonfb (%s): mapped %ldk videoram\n", pci_name(rinfo->pdev),
	       rinfo->mapped_vram/1024);

	/*
	 * Check for required workaround for PLL accesses

	 * so we can restore this upon __exit
	 */
	radeon_save_state (rinfo, &rinfo->init_state);
	memcpy(&rinfo->state, &rinfo->init_state, sizeof(struct radeon_regs));

	pci_set_drvdata(pdev, info);

	/* Setup Power Management capabilities */
	if (default_dynclk < -1) {
		/* -2 is special: means  ON on mobility chips and do not change on others */
		radeonfb_pm_init(rinfo, rinfo->is_mobility ? 1 : -1);
	} else
		radeonfb_pm_init(rinfo, default_dynclk);
		printk("radeonfb: Power Management enabled for Mobility chipsets\n");
	}

	/* Register with fbdev layer */
	ret = register_framebuffer(info);
	if (ret < 0) {
		printk (KERN_ERR "radeonfb (%s): could not register framebuffer\n",
			pci_name(rinfo->pdev));
		goto err_unmap_fb;
	}


	}
#endif

	printk ("radeonfb (%s): %s\n", pci_name(rinfo->pdev), rinfo->name);
		(rinfo->video_ram/(1024*1024)));

	if (rinfo->bios_seg)
		radeon_unmap_ROM(rinfo, pdev);

        if (!rinfo)
                return;
 
	radeonfb_pm_exit(rinfo);

	/* restore original state
	 * 
	 * Doesn't quite work yet, possibly because of the PPC hacking
	 * I do on startup, disable for now. --BenH
	 */
        radeon_write_mode (rinfo, &rinfo->init_state, 1);
 
	del_timer_sync(&rinfo->lvds_timer);


MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset");
MODULE_LICENSE("GPL");
module_param(noaccel, bool, 0);
module_param(default_dynclk, int, -2);
MODULE_PARM_DESC(default_dynclk, "int: -2=enable on mobility only,-1=do not change,0=off,1=on");
MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
module_param(nomodeset, bool, 0);
MODULE_PARM_DESC(nomodeset, "bool: disable actual setting of video mode");




#include <asm/pmac_feature.h>
#endif

/* For detecting supported PC laptops */
#ifdef CONFIG_X86
#include <linux/dmi.h>
#endif

#include "ati_ids.h"

#ifdef CONFIG_X86
/* This array holds a list of supported PC laptops.
 * Currently only few IBM models are tested.
 * If you want to experiment, use dmidecode to find out
 * vendor and product codes for Your laptop.
 */
static struct dmi_system_id __devinitdata radeonfb_dmi_table[] = {
	{
		/* Reported by George Avrunin <avrunin@math.umass.edu> */
		.ident = "IBM ThinkPad T40 (2372-9CU)",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
			DMI_MATCH(DMI_PRODUCT_NAME, "23729CU"),
		},
	},
	{
		/* Reported by Pete Toscano <pete@verisignlabs.com> */
		.ident = "IBM ThinkPad R40 (2722-B3G)",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
			DMI_MATCH(DMI_PRODUCT_NAME, "2722B3G"),
		},
	},
	{
		/* Reported by Klaus Kurzmann <mok@fluxnetz.de> */
		.ident = "IBM ThinkPad T40 (2373-25G)",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
			DMI_MATCH(DMI_PRODUCT_NAME, "237325G"),
		},
	},
	{
		/* Reported by Antti Andreimann <Antti.Andreimann@mail.ee> */
		.ident = "IBM ThinkPad T41 (2373-2FG)",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
			DMI_MATCH(DMI_PRODUCT_NAME, "23732FG"),
		},
	},
	{
		/* Reported by Antti P Miettinen <apm@brigitte.dna.fi> */
		.ident = "IBM ThinkPad T40 (2373-4G2)",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
			DMI_MATCH(DMI_PRODUCT_NAME, "23734G2"),
  	      },
	},
	{
		/* Reported by Pete Toscano <pete@verisignlabs.com> */
		.ident = "IBM ThinkPad T40 (2373-92G)",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
			DMI_MATCH(DMI_PRODUCT_NAME, "237392G"),
  	      },
	},
	{
		/* Reported by Pete Toscano <pete@verisignlabs.com> */
		.ident = "IBM ThinkPad T40 (2373-8CG)",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
			DMI_MATCH(DMI_PRODUCT_NAME, "23738CG"),
		},
	},
	{
		/* Reported by Pete Toscano <pete@verisignlabs.com> */
		.ident = "IBM ThinkPad T40 (2373-94U)",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
			DMI_MATCH(DMI_PRODUCT_NAME, "237394U"),
		},
	},
	{
		/* Reported by Manuel Carro <mcarro@fi.upm.es> */
		.ident = "IBM ThinkPad T40 (2373-94G)",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
			DMI_MATCH(DMI_PRODUCT_NAME, "237394G"),
		},
	},
	{
		/* Reported by Ajay Ramaswamy <ajay@ramaswamy.net> */
		.ident = "IBM ThinkPad T41 (2373-9HU)",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
			DMI_MATCH(DMI_PRODUCT_NAME, "23739HU"),
  	      },
	},
	{
		/* Reported by Jerome Poggi <Jerome.Poggi@hsc.fr> */
		.ident = "IBM ThinkPad T42 (2373-FWG)",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
			DMI_MATCH(DMI_PRODUCT_NAME, "2373FWG"),
		},
	},
	{
		/* Reported by Juerg Billeter <j@bitron.ch> */
		.ident = "IBM ThinkPad T40p (2373-G1G)",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
			DMI_MATCH(DMI_PRODUCT_NAME, "2373G1G"),
		},
	},
	{
		/* Reported by Hartwig, Thomas <t.hartwig@itth.com> */
		.ident = "IBM ThinkPad T40p (2373-G3G)",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
			DMI_MATCH(DMI_PRODUCT_NAME, "2373G3G"),
		},
	},
	{
		/* Reported by Eric Benson <eric_a_benson@yahoo.com> */
		.ident = "IBM ThinkPad T41p (2373-GEU)",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
			DMI_MATCH(DMI_PRODUCT_NAME, "2373GEU"),
		},
	},
	{
		/* Reported by Dwight Barkley <barkley@maths.warwick.ac.uk> */
		.ident = "IBM ThinkPad T42 (2373-JTU)",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
			DMI_MATCH(DMI_PRODUCT_NAME, "2373JTU"),
		},
	},
	{
		/* Reported by Vernon Mauery <vernux@us.ibm.com> */
		.ident = "IBM ThinkPad T40 (2373-MU4)",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
			DMI_MATCH(DMI_PRODUCT_NAME, "2373MU4"),
		},
	},
	{
		/* Reported by Ajay Ramaswamy <ajay@ramaswamy.net> */
		.ident = "IBM ThinkPad T41 (2373-XNX)",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
			DMI_MATCH(DMI_PRODUCT_NAME, "2373XNX"),
  	      },
	},
	{
		/* Reported by obi <graziano@cs.ucsb.edu> */
		.ident = "IBM ThinkPad T41 (2378-DEU)",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
			DMI_MATCH(DMI_PRODUCT_NAME, "2378DEU"),
		},
	},
	{
		/* Reported by Volker Braun <vbraun@physics.upenn.edu> */
		.ident = "IBM ThinkPad T41 (2379-DJU)",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
			DMI_MATCH(DMI_PRODUCT_NAME, "2379DJU"),
		},
	},
	{
		/* Reported by Pete Toscano <pete@verisignlabs.com> */
		.ident = "IBM ThinkPad T42 (2373-FWG)",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
			DMI_MATCH(DMI_PRODUCT_NAME, "2373FWG"),
		},
	},
	{
		/* Reported by tonne2004@gehheimdienst.de */
		.ident = "IBM ThinkPad R40 (2722-3GG)",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
			DMI_MATCH(DMI_PRODUCT_NAME, "27223GG"),
		},
	},
	{
		/* Reported by Nils Trebing <nils.trebing@uni-konstanz.de> */
		.ident = "IBM ThinkPad R40 (2722-5MG)",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
			DMI_MATCH(DMI_PRODUCT_NAME, "27225MG"),
		},
	},
	{ },
	/* Negative reports: */
	/* IBM thinkpad T30 2366 -> machine hangs 
           Reported by: Jakob Schiotz <schiotz@fysik.dtu.dk> */
	/* IBM thinkpad T42p 2373-KUU -> machine hangs as X starts
           Reported by: Dax Kelson <dax@gurulabs.com> */
};

extern int radeon_force_sleep;
#endif

void radeon_pm_disable_dynamic_mode(struct radeonfb_info *rinfo)
{
	u32 tmp;

	tmp = INPLL( pllMCLK_MISC) | MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND;
	OUTPLL( pllMCLK_MISC, tmp);
	
 	/* BUS_CNTL1__MOBILE_PLATORM_SEL setting is northbridge chipset
 	 * and radeon chip dependent. Thus we only enable it on Mac for
 	 * now (until we get more info on how to compute the correct 
 	 * value for various X86 bridges).
 	 */
 
#ifdef CONFIG_PPC_PMAC
	/* AGP PLL control */
	if (rinfo->family <= CHIP_FAMILY_RV280) {
		OUTREG(BUS_CNTL1, INREG(BUS_CNTL1) |  BUS_CNTL1__AGPCLK_VALID);

		OUTREG(BUS_CNTL1, INREG(BUS_CNTL1));
		OUTREG(BUS_CNTL1, (INREG(BUS_CNTL1) & ~0x4000) | 0x8000);
	}
#endif

	OUTREG(CRTC_OFFSET_CNTL, (INREG(CRTC_OFFSET_CNTL)
				  & ~CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN));

		OUTREG(TV_DAC_CNTL, INREG(TV_DAC_CNTL) | 0x07000000);
	}
#endif /* defined(CONFIG_PM) && defined(CONFIG_PPC_OF) */

/* The PM code also works on some PC laptops.
 * Only a few models are actually tested so Your mileage may vary.
 * We can do D2 on at least M7 and M9 on some IBM ThinkPad T41 models.
 */
#if defined(CONFIG_PM) && defined(CONFIG_X86)
	if (radeon_force_sleep || dmi_check_system(radeonfb_dmi_table)) {
		if (radeon_force_sleep)
			printk("radeonfb: forcefully enabling sleep mode\n");
		else
			printk("radeonfb: enabling sleep mode\n");

		if (rinfo->is_mobility && rinfo->pm_reg &&
		    rinfo->family <= CHIP_FAMILY_RV250)
			rinfo->pm_mode |= radeon_pm_d2;

		/* Power down TV DAC, that saves a significant amount of power,
		 * we'll have something better once we actually have some TVOut
		 * support
		 */
		OUTREG(TV_DAC_CNTL, INREG(TV_DAC_CNTL) | 0x07000000);
	}
#endif /* defined(CONFIG_PM) && defined(CONFIG_X86) */
}

void radeonfb_pm_exit(struct radeonfb_info *rinfo)

Return to bug 3022

Lines 25-32 Link Here

(-)linux-2.6.10-old/drivers/video/aty/radeon_pm.c (+230 lines)
25	#include <asm/pmac_feature.h>	25	#include <asm/pmac_feature.h>
26	#endif	26	#endif
27		27
		28	/* For detecting supported PC laptops */
		29	#ifdef CONFIG_X86
		30	#include <linux/dmi.h>
		31	#endif
		32
28	#include "ati_ids.h"	33	#include "ati_ids.h"
29		34
		35	#ifdef CONFIG_X86
		36	/* This array holds a list of supported PC laptops.
		37	* Currently only few IBM models are tested.
		38	* If you want to experiment, use dmidecode to find out
		39	* vendor and product codes for Your laptop.
		40	*/
		41	static struct dmi_system_id __devinitdata radeonfb_dmi_table[] = {
		42	{
		43	/* Reported by George Avrunin <avrunin@math.umass.edu> */
		44	.ident = "IBM ThinkPad T40 (2372-9CU)",
		45	.matches = {
		46	DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
		47	DMI_MATCH(DMI_PRODUCT_NAME, "23729CU"),
		48	},
		49	},
		50	{
		51	/* Reported by Pete Toscano <pete@verisignlabs.com> */
		52	.ident = "IBM ThinkPad R40 (2722-B3G)",
		53	.matches = {
		54	DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
		55	DMI_MATCH(DMI_PRODUCT_NAME, "2722B3G"),
		56	},
		57	},
		58	{
		59	/* Reported by Klaus Kurzmann <mok@fluxnetz.de> */
		60	.ident = "IBM ThinkPad T40 (2373-25G)",
		61	.matches = {
		62	DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
		63	DMI_MATCH(DMI_PRODUCT_NAME, "237325G"),
		64	},
		65	},
		66	{
		67	/* Reported by Antti Andreimann <Antti.Andreimann@mail.ee> */
		68	.ident = "IBM ThinkPad T41 (2373-2FG)",
		69	.matches = {
		70	DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
		71	DMI_MATCH(DMI_PRODUCT_NAME, "23732FG"),
		72	},
		73	},
		74	{
		75	/* Reported by Antti P Miettinen <apm@brigitte.dna.fi> */
		76	.ident = "IBM ThinkPad T40 (2373-4G2)",
		77	.matches = {
		78	DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
		79	DMI_MATCH(DMI_PRODUCT_NAME, "23734G2"),
		80	},
		81	},
		82	{
		83	/* Reported by Pete Toscano <pete@verisignlabs.com> */
		84	.ident = "IBM ThinkPad T40 (2373-92G)",
		85	.matches = {
		86	DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
		87	DMI_MATCH(DMI_PRODUCT_NAME, "237392G"),
		88	},
		89	},
		90	{
		91	/* Reported by Pete Toscano <pete@verisignlabs.com> */
		92	.ident = "IBM ThinkPad T40 (2373-8CG)",
		93	.matches = {
		94	DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
		95	DMI_MATCH(DMI_PRODUCT_NAME, "23738CG"),
		96	},
		97	},
		98	{
99	/* Reported by Pete Toscano <pete@verisignlabs.com> */
100	.ident = "IBM ThinkPad T40 (2373-94U)",
101	.matches = {
102	DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
103	DMI_MATCH(DMI_PRODUCT_NAME, "237394U"),
104	},
105	},
106	{
107	/* Reported by Manuel Carro <mcarro@fi.upm.es> */
108	.ident = "IBM ThinkPad T40 (2373-94G)",
109	.matches = {
110	DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
111	DMI_MATCH(DMI_PRODUCT_NAME, "237394G"),
112	},
113	},
114	{
115	/* Reported by Ajay Ramaswamy <ajay@ramaswamy.net> */
116	.ident = "IBM ThinkPad T41 (2373-9HU)",
117	.matches = {
118	DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
119	DMI_MATCH(DMI_PRODUCT_NAME, "23739HU"),
120	},
121	},
122	{
123	/* Reported by Jerome Poggi <Jerome.Poggi@hsc.fr> */
124	.ident = "IBM ThinkPad T42 (2373-FWG)",
125	.matches = {
126	DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
127	DMI_MATCH(DMI_PRODUCT_NAME, "2373FWG"),
128	},
129	},
130	{
131	/* Reported by Juerg Billeter <j@bitron.ch> */
132	.ident = "IBM ThinkPad T40p (2373-G1G)",
133	.matches = {
134	DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
135	DMI_MATCH(DMI_PRODUCT_NAME, "2373G1G"),
136	},
137	},
138	{
139	/* Reported by Hartwig, Thomas <t.hartwig@itth.com> */
140	.ident = "IBM ThinkPad T40p (2373-G3G)",
141	.matches = {
142	DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
143	DMI_MATCH(DMI_PRODUCT_NAME, "2373G3G"),
144	},
145	},
146	{
147	/* Reported by Eric Benson <eric_a_benson@yahoo.com> */
148	.ident = "IBM ThinkPad T41p (2373-GEU)",
149	.matches = {
150	DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
151	DMI_MATCH(DMI_PRODUCT_NAME, "2373GEU"),
152	},
153	},
154	{
155	/* Reported by Dwight Barkley <barkley@maths.warwick.ac.uk> */
156	.ident = "IBM ThinkPad T42 (2373-JTU)",
157	.matches = {
158	DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
159	DMI_MATCH(DMI_PRODUCT_NAME, "2373JTU"),
160	},
161	},
162	{
163	/* Reported by Vernon Mauery <vernux@us.ibm.com> */
164	.ident = "IBM ThinkPad T40 (2373-MU4)",
165	.matches = {
166	DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
167	DMI_MATCH(DMI_PRODUCT_NAME, "2373MU4"),
168	},
169	},
170	{
171	/* Reported by Ajay Ramaswamy <ajay@ramaswamy.net> */
172	.ident = "IBM ThinkPad T41 (2373-XNX)",
173	.matches = {
174	DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
175	DMI_MATCH(DMI_PRODUCT_NAME, "2373XNX"),
176	},
177	},
178	{
179	/* Reported by obi <graziano@cs.ucsb.edu> */
180	.ident = "IBM ThinkPad T41 (2378-DEU)",
181	.matches = {
182	DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
183	DMI_MATCH(DMI_PRODUCT_NAME, "2378DEU"),
184	},
185	},
186	{
187	/* Reported by Volker Braun <vbraun@physics.upenn.edu> */
188	.ident = "IBM ThinkPad T41 (2379-DJU)",
189	.matches = {
190	DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
191	DMI_MATCH(DMI_PRODUCT_NAME, "2379DJU"),
192	},
193	},
194	{
195	/* Reported by Pete Toscano <pete@verisignlabs.com> */
196	.ident = "IBM ThinkPad T42 (2373-FWG)",
197	.matches = {
198	DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
199	DMI_MATCH(DMI_PRODUCT_NAME, "2373FWG"),
200	},
201	},
202	{
203	/* Reported by tonne2004@gehheimdienst.de */
204	.ident = "IBM ThinkPad R40 (2722-3GG)",
205	.matches = {
206	DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
207	DMI_MATCH(DMI_PRODUCT_NAME, "27223GG"),
208	},
209	},
210	{
211	/* Reported by Nils Trebing <nils.trebing@uni-konstanz.de> */
212	.ident = "IBM ThinkPad R40 (2722-5MG)",
213	.matches = {
214	DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
215	DMI_MATCH(DMI_PRODUCT_NAME, "27225MG"),
216	},
217	},
218	{ },
219	/* Negative reports: */
220	/* IBM thinkpad T30 2366 -> machine hangs
221	Reported by: Jakob Schiotz <schiotz@fysik.dtu.dk> */
222	/* IBM thinkpad T42p 2373-KUU -> machine hangs as X starts
223	Reported by: Dax Kelson <dax@gurulabs.com> */
224	};
225
226	extern int radeon_force_sleep;
227	#endif
228
30	void radeon_pm_disable_dynamic_mode(struct radeonfb_info *rinfo)	229	void radeon_pm_disable_dynamic_mode(struct radeonfb_info *rinfo)
31	{	230	{
32	u32 tmp;	231	u32 tmp;
Lines 853-858 Link Here
853	tmp = INPLL( pllMCLK_MISC) \| MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND;	1052	tmp = INPLL( pllMCLK_MISC) \| MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND;
854	OUTPLL( pllMCLK_MISC, tmp);	1053	OUTPLL( pllMCLK_MISC, tmp);
855		1054
		1055	/* BUS_CNTL1__MOBILE_PLATORM_SEL setting is northbridge chipset
		1056	* and radeon chip dependent. Thus we only enable it on Mac for
		1057	* now (until we get more info on how to compute the correct
		1058	* value for various X86 bridges).
		1059	*/
		1060
		1061	#ifdef CONFIG_PPC_PMAC
856	/* AGP PLL control */	1062	/* AGP PLL control */
857	if (rinfo->family <= CHIP_FAMILY_RV280) {	1063	if (rinfo->family <= CHIP_FAMILY_RV280) {
858	OUTREG(BUS_CNTL1, INREG(BUS_CNTL1) \| BUS_CNTL1__AGPCLK_VALID);	1064	OUTREG(BUS_CNTL1, INREG(BUS_CNTL1) \| BUS_CNTL1__AGPCLK_VALID);
Lines 864-869 Link Here
864	OUTREG(BUS_CNTL1, INREG(BUS_CNTL1));	1070	OUTREG(BUS_CNTL1, INREG(BUS_CNTL1));
865	OUTREG(BUS_CNTL1, (INREG(BUS_CNTL1) & ~0x4000) \| 0x8000);	1071	OUTREG(BUS_CNTL1, (INREG(BUS_CNTL1) & ~0x4000) \| 0x8000);
866	}	1072	}
		1073	#endif
867		1074
868	OUTREG(CRTC_OFFSET_CNTL, (INREG(CRTC_OFFSET_CNTL)	1075	OUTREG(CRTC_OFFSET_CNTL, (INREG(CRTC_OFFSET_CNTL)
869	& ~CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN));	1076	& ~CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN));
Lines 2748-2753 Link Here
2748	OUTREG(TV_DAC_CNTL, INREG(TV_DAC_CNTL) \| 0x07000000);	2955	OUTREG(TV_DAC_CNTL, INREG(TV_DAC_CNTL) \| 0x07000000);
2749	}	2956	}
2750	#endif /* defined(CONFIG_PM) && defined(CONFIG_PPC_OF) */	2957	#endif /* defined(CONFIG_PM) && defined(CONFIG_PPC_OF) */
		2958
		2959	/* The PM code also works on some PC laptops.
		2960	* Only a few models are actually tested so Your mileage may vary.
		2961	* We can do D2 on at least M7 and M9 on some IBM ThinkPad T41 models.
		2962	*/
		2963	#if defined(CONFIG_PM) && defined(CONFIG_X86)
		2964	if (radeon_force_sleep \|\| dmi_check_system(radeonfb_dmi_table)) {
		2965	if (radeon_force_sleep)
		2966	printk("radeonfb: forcefully enabling sleep mode\n");
		2967	else
		2968	printk("radeonfb: enabling sleep mode\n");
		2969
		2970	if (rinfo->is_mobility && rinfo->pm_reg &&
		2971	rinfo->family <= CHIP_FAMILY_RV250)
		2972	rinfo->pm_mode \|= radeon_pm_d2;
		2973
		2974	/* Power down TV DAC, that saves a significant amount of power,
		2975	* we'll have something better once we actually have some TVOut
		2976	* support
		2977	*/
		2978	OUTREG(TV_DAC_CNTL, INREG(TV_DAC_CNTL) \| 0x07000000);
		2979	}
		2980	#endif /* defined(CONFIG_PM) && defined(CONFIG_X86) */
2751	}	2981	}
2752		2982
2753	void radeonfb_pm_exit(struct radeonfb_info *rinfo)	2983	void radeonfb_pm_exit(struct radeonfb_info *rinfo)