|
Lines 862-867
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|
| 862 |
.pin_config_group_set = amd_pinconf_group_set, |
862 |
.pin_config_group_set = amd_pinconf_group_set, |
| 863 |
}; |
863 |
}; |
| 864 |
|
864 |
|
|
|
865 |
static void amd_gpio_irq_init(struct amd_gpio *gpio_dev) |
| 866 |
{ |
| 867 |
struct pinctrl_desc *desc = gpio_dev->pctrl->desc; |
| 868 |
unsigned long flags; |
| 869 |
u32 pin_reg, mask; |
| 870 |
int i; |
| 871 |
|
| 872 |
mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) | |
| 873 |
BIT(INTERRUPT_MASK_OFF) | BIT(INTERRUPT_ENABLE_OFF) | |
| 874 |
BIT(WAKE_CNTRL_OFF_S4); |
| 875 |
|
| 876 |
for (i = 0; i < desc->npins; i++) { |
| 877 |
int pin = desc->pins[i].number; |
| 878 |
const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin); |
| 879 |
|
| 880 |
if (!pd) |
| 881 |
continue; |
| 882 |
|
| 883 |
raw_spin_lock_irqsave(&gpio_dev->lock, flags); |
| 884 |
|
| 885 |
pin_reg = readl(gpio_dev->base + i * 4); |
| 886 |
pin_reg &= ~mask; |
| 887 |
writel(pin_reg, gpio_dev->base + i * 4); |
| 888 |
|
| 889 |
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
| 890 |
} |
| 891 |
} |
| 892 |
|
| 865 |
#ifdef CONFIG_PM_SLEEP |
893 |
#ifdef CONFIG_PM_SLEEP |
| 866 |
static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin) |
894 |
static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin) |
| 867 |
{ |
895 |
{ |
|
Lines 1099-1104
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|
| 1099 |
return PTR_ERR(gpio_dev->pctrl); |
1127 |
return PTR_ERR(gpio_dev->pctrl); |
| 1100 |
} |
1128 |
} |
| 1101 |
|
1129 |
|
|
|
1130 |
/* Disable and mask interrupts */ |
| 1131 |
amd_gpio_irq_init(gpio_dev); |
| 1132 |
|
| 1102 |
girq = &gpio_dev->gc.irq; |
1133 |
girq = &gpio_dev->gc.irq; |
| 1103 |
gpio_irq_chip_set_chip(girq, &amd_gpio_irqchip); |
1134 |
gpio_irq_chip_set_chip(girq, &amd_gpio_irqchip); |
| 1104 |
/* This will let us handle the parent IRQ in the driver */ |
1135 |
/* This will let us handle the parent IRQ in the driver */ |