Attachment #19642 for bug #12345

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Lines 137-142 typedef struct drm_i915_private { Link Here

(-)a/drivers/gpu/drm/i915/i915_drv.h (+1 lines)
137	/** Cached value of IMR to avoid reads in updating the bitfield */	137	/** Cached value of IMR to avoid reads in updating the bitfield */
138	u32 irq_mask_reg;	138	u32 irq_mask_reg;
139	u32 pipestat[2];	139	u32 pipestat[2];
		140	int vblankstat[2];
140		141
141	int tex_lru_log_granularity;	142	int tex_lru_log_granularity;
142	int allow_batchbuffer;	143	int allow_batchbuffer;

Lines 408-413 int i915_enable_vblank(struct drm_device *dev, int pipe) Link Here

(-)a/drivers/gpu/drm/i915/i915_irq.c (+12 lines)
408	else	408	else
409	i915_enable_pipestat(dev_priv, pipe,	409	i915_enable_pipestat(dev_priv, pipe,
410	PIPE_VBLANK_INTERRUPT_ENABLE);	410	PIPE_VBLANK_INTERRUPT_ENABLE);
		411	if (pipe == 0 \|\| pipe == 1)
		412	dev_priv->vblankstat[pipe] = 1;
		413
411	spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);	414	spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
412	return 0;	415	return 0;
413	}	416	}
Lines 424-429 void i915_disable_vblank(struct drm_device *dev, int pipe) Link Here
424	i915_disable_pipestat(dev_priv, pipe,	427	i915_disable_pipestat(dev_priv, pipe,
425	PIPE_VBLANK_INTERRUPT_ENABLE \|	428	PIPE_VBLANK_INTERRUPT_ENABLE \|
426	PIPE_START_VBLANK_INTERRUPT_ENABLE);	429	PIPE_START_VBLANK_INTERRUPT_ENABLE);
		430
		431	if (pipe == 0 \|\| pipe == 1)
		432	dev_priv->vblankstat[pipe] = 0;
		433
427	spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);	434	spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
428	}	435	}
429		436
Lines 522-527 int i915_driver_irq_postinstall(struct drm_device *dev) Link Here
522	opregion_enable_asle(dev);	529	opregion_enable_asle(dev);
523	DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);	530	DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
524		531
		532	if (dev_priv->vblankstat[0] == 1)
		533	i915_enable_vblank(dev, 0);
		534	if (dev_priv->vblankstat[1] == 1)
		535	i915_enable_vblank(dev, 1);
		536
525	return 0;	537	return 0;
526	}	538	}
527		539

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