Attachment #175281 for bug #63661




{
	struct pci_dev *child;
	struct pci_bus *linkbus = link->pdev->subordinate;
	u32 val = enable ? PCI_EXP_LNKCTL_CLKREQ_EN : 0;

	list_for_each_entry(child, &linkbus->devices, bus_list)
		pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL,
						   PCI_EXP_LNKCTL_CLKREQ_EN,
						   val);
		else
			pcie_capability_clear_word(child, PCI_EXP_LNKCTL,
						   PCI_EXP_LNKCTL_CLKREQ_EN);
	}
	link->clkpm_enabled = !!enable;
}

   debug




	struct pci_bus *linkbus = link->pdev->subordinate;
	u32 val = enable ? PCI_EXP_LNKCTL_CLKREQ_EN : 0;

	list_for_each_entry(child, &linkbus->devices, bus_list) {
dev_info(&child->dev, "wr PCI_EXP_LNKCTL clear %#010x set %#010x (%s)\n", PCI_EXP_LNKCTL_CLKREQ_EN, val, __func__);
		pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL,
						   PCI_EXP_LNKCTL_CLKREQ_EN,
						   val);
	}
	link->clkpm_enabled = !!enable;
}


	/* All functions should have the same cap and state, take the worst */
	list_for_each_entry(child, &linkbus->devices, bus_list) {
		pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &reg32);
dev_info(&child->dev, "rd PCI_EXP_LNKCAP %#010x (%s)\n", reg32, __func__);
		if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) {
			capable = 0;
			enabled = 0;
			break;
		}
		pcie_capability_read_word(child, PCI_EXP_LNKCTL, &reg16);
dev_info(&child->dev, "rd PCI_EXP_LNKCTL %#06x (%s)\n", reg16, __func__);
		if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN))
			enabled = 0;
	}


	/* Check downstream component if bit Slot Clock Configuration is 1 */
	pcie_capability_read_word(child, PCI_EXP_LNKSTA, &reg16);
dev_info(&child->dev, "rd PCI_EXP_LNKSTA %#06x (%s)\n", reg16, __func__);
	if (!(reg16 & PCI_EXP_LNKSTA_SLC))
		same_clock = 0;

	/* Check upstream component if bit Slot Clock Configuration is 1 */
	pcie_capability_read_word(parent, PCI_EXP_LNKSTA, &reg16);
dev_info(&parent->dev, "rd PCI_EXP_LNKSTA %#06x (%s)\n", reg16, __func__);
	if (!(reg16 & PCI_EXP_LNKSTA_SLC))
		same_clock = 0;

	/* Configure downstream component, all functions */
	list_for_each_entry(child, &linkbus->devices, bus_list) {
		pcie_capability_read_word(child, PCI_EXP_LNKCTL, &reg16);
dev_info(&child->dev, "rd PCI_EXP_LNKCTL %#06x (%s)\n", reg16, __func__);
		child_reg[PCI_FUNC(child->devfn)] = reg16;
		if (same_clock)
			reg16 |= PCI_EXP_LNKCTL_CCC;
		else
			reg16 &= ~PCI_EXP_LNKCTL_CCC;
dev_info(&child->dev, "wr PCI_EXP_LNKCTL %#06x (%s)\n", reg16, __func__);
		pcie_capability_write_word(child, PCI_EXP_LNKCTL, reg16);
	}

	/* Configure upstream component */
	pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &reg16);
dev_info(&parent->dev, "rd PCI_EXP_LNKCTL %#06x (%s)\n", reg16, __func__);
	parent_reg = reg16;
	if (same_clock)
		reg16 |= PCI_EXP_LNKCTL_CCC;
	else
		reg16 &= ~PCI_EXP_LNKCTL_CCC;
dev_info(&parent->dev, "wr PCI_EXP_LNKCTL %#06x (%s)\n", reg16, __func__);
	pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);

	/* Retrain link */
	reg16 |= PCI_EXP_LNKCTL_RL;
dev_info(&parent->dev, "wr PCI_EXP_LNKCTL %#06x (%s)\n", reg16, __func__);
	pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);

	/* Wait for link training end. Break out after waiting for timeout */


	/* Training failed. Restore common clock configurations */
	dev_err(&parent->dev, "ASPM: Could not configure common clock\n");
	list_for_each_entry(child, &linkbus->devices, bus_list) {
dev_info(&child->dev, "wr PCI_EXP_LNKCTL %#06x (%s)\n", child_reg[PCI_FUNC(child->devfn)], __func__);
		pcie_capability_write_word(child, PCI_EXP_LNKCTL,
					   child_reg[PCI_FUNC(child->devfn)]);
	}
dev_info(&parent->dev, "wr PCI_EXP_LNKCTL %#06x (%s)\n", parent_reg, __func__);
	pcie_capability_write_word(parent, PCI_EXP_LNKCTL, parent_reg);
}


	u32 reg32;

	pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &reg32);
dev_info(&pdev->dev, "rd PCI_EXP_LNKCAP %#010x (%s)\n", reg32, __func__);
	info->support = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10;
	info->latency_encoding_l0s = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12;
	info->latency_encoding_l1  = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15;
	pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &reg16);
dev_info(&pdev->dev, "rd PCI_EXP_LNKCTL %#06x (%s)\n", reg16, __func__);
	info->enabled = reg16 & PCI_EXP_LNKCTL_ASPMC;
}


			continue;

		pcie_capability_read_dword(child, PCI_EXP_DEVCAP, &reg32);
dev_info(&child->dev, "rd PCI_EXP_DEVCAP %#010x (%s)\n", reg32, __func__);
		/* Calculate endpoint L0s acceptable latency */
		encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6;
		acceptable->l0s = calc_l0s_acceptable(encoding);


static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)
{
dev_info(&pdev->dev, "wr PCI_EXP_LNKCTL clear %#010x set %#010x (%s)\n", PCI_EXP_LNKCTL_ASPMC, val, __func__);
	pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL,
					   PCI_EXP_LNKCTL_ASPMC, val);
}

		 * RBER bit to determine if a function is 1.1 version device
		 */
		pcie_capability_read_dword(child, PCI_EXP_DEVCAP, &reg32);
dev_info(&child->dev, "rd PCI_EXP_DEVCAP %#010x (%s)\n", reg32, __func__);
		if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) {
			dev_info(&child->dev, "disabling ASPM on pre-1.1 PCIe device.  You can enable it with 'pcie_aspm=force'\n");
			return -EINVAL;

Lines 349-354 int pci_enable_resources(struct pci_dev *dev, int mask) Link Here

(-)a/drivers/pci/setup-res.c (+2 lines)
349	struct resource *r;	349	struct resource *r;
350		350
351	pci_read_config_word(dev, PCI_COMMAND, &cmd);	351	pci_read_config_word(dev, PCI_COMMAND, &cmd);
		352	dev_info(&dev->dev, "rd PCI_COMMAND %#06x (%s)\n", cmd, __func__);
352	old_cmd = cmd;	353	old_cmd = cmd;
353		354
354	for (i = 0; i < PCI_NUM_RESOURCES; i++) {	355	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
Lines 384-389 int pci_enable_resources(struct pci_dev *dev, int mask) Link Here
384	if (cmd != old_cmd) {	385	if (cmd != old_cmd) {
385	dev_info(&dev->dev, "enabling device (%04x -> %04x)\n",	386	dev_info(&dev->dev, "enabling device (%04x -> %04x)\n",
386	old_cmd, cmd);	387	old_cmd, cmd);
		388	dev_info(&dev->dev, "wr PCI_COMMAND %#06x (%s)\n", cmd, __func__);
387	pci_write_config_word(dev, PCI_COMMAND, cmd);	389	pci_write_config_word(dev, PCI_COMMAND, cmd);
388	}	390	}
389	return 0;	391	return 0;

Return to bug 63661

Lines 127-141 static void pcie_set_clkpm_nocheck(struct pcie_link_state *link, int enable) Link Here

(-)a/drivers/pci/pcie/aspm.c (-8 / +5 lines)
127	{	127	{
128	struct pci_dev *child;	128	struct pci_dev *child;
129	struct pci_bus *linkbus = link->pdev->subordinate;	129	struct pci_bus *linkbus = link->pdev->subordinate;
		130	u32 val = enable ? PCI_EXP_LNKCTL_CLKREQ_EN : 0;
130		131
131	list_for_each_entry(child, &linkbus->devices, bus_list) {	132	list_for_each_entry(child, &linkbus->devices, bus_list)
132	if (enable)	133	pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL,
133	pcie_capability_set_word(child, PCI_EXP_LNKCTL,	134	PCI_EXP_LNKCTL_CLKREQ_EN,
134	PCI_EXP_LNKCTL_CLKREQ_EN);	135	val);
135	else
136	pcie_capability_clear_word(child, PCI_EXP_LNKCTL,
137	PCI_EXP_LNKCTL_CLKREQ_EN);
138	}
139	link->clkpm_enabled = !!enable;	136	link->clkpm_enabled = !!enable;
140	}	137	}
141		138
142	debug	139	debug

Lines 129-138 static void pcie_set_clkpm_nocheck(struct pcie_link_state *link, int enable) Link Here

(-)a/drivers/pci/pcie/aspm.c (-2 / +21 lines)
129	struct pci_bus *linkbus = link->pdev->subordinate;	129	struct pci_bus *linkbus = link->pdev->subordinate;
130	u32 val = enable ? PCI_EXP_LNKCTL_CLKREQ_EN : 0;	130	u32 val = enable ? PCI_EXP_LNKCTL_CLKREQ_EN : 0;
131		131
132	list_for_each_entry(child, &linkbus->devices, bus_list)	132	list_for_each_entry(child, &linkbus->devices, bus_list) {
		133	dev_info(&child->dev, "wr PCI_EXP_LNKCTL clear %#010x set %#010x (%s)\n", PCI_EXP_LNKCTL_CLKREQ_EN, val, __func__);
133	pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL,	134	pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL,
134	PCI_EXP_LNKCTL_CLKREQ_EN,	135	PCI_EXP_LNKCTL_CLKREQ_EN,
135	val);	136	val);
		137	}
136	link->clkpm_enabled = !!enable;	138	link->clkpm_enabled = !!enable;
137	}	139	}
138		140
Lines 158-169 static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist) Link Here
158	/* All functions should have the same cap and state, take the worst */	160	/* All functions should have the same cap and state, take the worst */
159	list_for_each_entry(child, &linkbus->devices, bus_list) {	161	list_for_each_entry(child, &linkbus->devices, bus_list) {
160	pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &reg32);	162	pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &reg32);
		163	dev_info(&child->dev, "rd PCI_EXP_LNKCAP %#010x (%s)\n", reg32, __func__);
161	if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) {	164	if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) {
162	capable = 0;	165	capable = 0;
163	enabled = 0;	166	enabled = 0;
164	break;	167	break;
165	}	168	}
166	pcie_capability_read_word(child, PCI_EXP_LNKCTL, &reg16);	169	pcie_capability_read_word(child, PCI_EXP_LNKCTL, &reg16);
		170	dev_info(&child->dev, "rd PCI_EXP_LNKCTL %#06x (%s)\n", reg16, __func__);
167	if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN))	171	if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN))
168	enabled = 0;	172	enabled = 0;
169	}	173	}
Lines 193-228 static void pcie_aspm_configure_common_clock(struct pcie_link_state *link) Link Here
193		197
194	/* Check downstream component if bit Slot Clock Configuration is 1 */	198	/* Check downstream component if bit Slot Clock Configuration is 1 */
195	pcie_capability_read_word(child, PCI_EXP_LNKSTA, &reg16);	199	pcie_capability_read_word(child, PCI_EXP_LNKSTA, &reg16);
		200	dev_info(&child->dev, "rd PCI_EXP_LNKSTA %#06x (%s)\n", reg16, __func__);
196	if (!(reg16 & PCI_EXP_LNKSTA_SLC))	201	if (!(reg16 & PCI_EXP_LNKSTA_SLC))
197	same_clock = 0;	202	same_clock = 0;
198		203
199	/* Check upstream component if bit Slot Clock Configuration is 1 */	204	/* Check upstream component if bit Slot Clock Configuration is 1 */
200	pcie_capability_read_word(parent, PCI_EXP_LNKSTA, &reg16);	205	pcie_capability_read_word(parent, PCI_EXP_LNKSTA, &reg16);
		206	dev_info(&parent->dev, "rd PCI_EXP_LNKSTA %#06x (%s)\n", reg16, __func__);
201	if (!(reg16 & PCI_EXP_LNKSTA_SLC))	207	if (!(reg16 & PCI_EXP_LNKSTA_SLC))
202	same_clock = 0;	208	same_clock = 0;
203		209
204	/* Configure downstream component, all functions */	210	/* Configure downstream component, all functions */
205	list_for_each_entry(child, &linkbus->devices, bus_list) {	211	list_for_each_entry(child, &linkbus->devices, bus_list) {
206	pcie_capability_read_word(child, PCI_EXP_LNKCTL, &reg16);	212	pcie_capability_read_word(child, PCI_EXP_LNKCTL, &reg16);
		213	dev_info(&child->dev, "rd PCI_EXP_LNKCTL %#06x (%s)\n", reg16, __func__);
207	child_reg[PCI_FUNC(child->devfn)] = reg16;	214	child_reg[PCI_FUNC(child->devfn)] = reg16;
208	if (same_clock)	215	if (same_clock)
209	reg16 \|= PCI_EXP_LNKCTL_CCC;	216	reg16 \|= PCI_EXP_LNKCTL_CCC;
210	else	217	else
211	reg16 &= ~PCI_EXP_LNKCTL_CCC;	218	reg16 &= ~PCI_EXP_LNKCTL_CCC;
		219	dev_info(&child->dev, "wr PCI_EXP_LNKCTL %#06x (%s)\n", reg16, __func__);
212	pcie_capability_write_word(child, PCI_EXP_LNKCTL, reg16);	220	pcie_capability_write_word(child, PCI_EXP_LNKCTL, reg16);
213	}	221	}
214		222
215	/* Configure upstream component */	223	/* Configure upstream component */
216	pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &reg16);	224	pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &reg16);
		225	dev_info(&parent->dev, "rd PCI_EXP_LNKCTL %#06x (%s)\n", reg16, __func__);
217	parent_reg = reg16;	226	parent_reg = reg16;
218	if (same_clock)	227	if (same_clock)
219	reg16 \|= PCI_EXP_LNKCTL_CCC;	228	reg16 \|= PCI_EXP_LNKCTL_CCC;
220	else	229	else
221	reg16 &= ~PCI_EXP_LNKCTL_CCC;	230	reg16 &= ~PCI_EXP_LNKCTL_CCC;
		231	dev_info(&parent->dev, "wr PCI_EXP_LNKCTL %#06x (%s)\n", reg16, __func__);
222	pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);	232	pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
223		233
224	/* Retrain link */	234	/* Retrain link */
225	reg16 \|= PCI_EXP_LNKCTL_RL;	235	reg16 \|= PCI_EXP_LNKCTL_RL;
		236	dev_info(&parent->dev, "wr PCI_EXP_LNKCTL %#06x (%s)\n", reg16, __func__);
226	pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);	237	pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
227		238
228	/* Wait for link training end. Break out after waiting for timeout */	239	/* Wait for link training end. Break out after waiting for timeout */
Lines 240-248 static void pcie_aspm_configure_common_clock(struct pcie_link_state *link) Link Here
240		251
241	/* Training failed. Restore common clock configurations */	252	/* Training failed. Restore common clock configurations */
242	dev_err(&parent->dev, "ASPM: Could not configure common clock\n");	253	dev_err(&parent->dev, "ASPM: Could not configure common clock\n");
243	list_for_each_entry(child, &linkbus->devices, bus_list)	254	list_for_each_entry(child, &linkbus->devices, bus_list) {
		255	dev_info(&child->dev, "wr PCI_EXP_LNKCTL %#06x (%s)\n", child_reg[PCI_FUNC(child->devfn)], __func__);
244	pcie_capability_write_word(child, PCI_EXP_LNKCTL,	256	pcie_capability_write_word(child, PCI_EXP_LNKCTL,
245	child_reg[PCI_FUNC(child->devfn)]);	257	child_reg[PCI_FUNC(child->devfn)]);
		258	}
		259	dev_info(&parent->dev, "wr PCI_EXP_LNKCTL %#06x (%s)\n", parent_reg, __func__);
246	pcie_capability_write_word(parent, PCI_EXP_LNKCTL, parent_reg);	260	pcie_capability_write_word(parent, PCI_EXP_LNKCTL, parent_reg);
247	}	261	}
248		262
Lines 292-301 static void pcie_get_aspm_reg(struct pci_dev *pdev, Link Here
292	u32 reg32;	306	u32 reg32;
293		307
294	pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &reg32);	308	pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &reg32);
		309	dev_info(&pdev->dev, "rd PCI_EXP_LNKCAP %#010x (%s)\n", reg32, __func__);
295	info->support = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10;	310	info->support = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10;
296	info->latency_encoding_l0s = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12;	311	info->latency_encoding_l0s = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12;
297	info->latency_encoding_l1 = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15;	312	info->latency_encoding_l1 = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15;
298	pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &reg16);	313	pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &reg16);
		314	dev_info(&pdev->dev, "rd PCI_EXP_LNKCTL %#06x (%s)\n", reg16, __func__);
299	info->enabled = reg16 & PCI_EXP_LNKCTL_ASPMC;	315	info->enabled = reg16 & PCI_EXP_LNKCTL_ASPMC;
300	}	316	}
301		317
Lines 410-415 static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) Link Here
410	continue;	426	continue;
411		427
412	pcie_capability_read_dword(child, PCI_EXP_DEVCAP, &reg32);	428	pcie_capability_read_dword(child, PCI_EXP_DEVCAP, &reg32);
		429	dev_info(&child->dev, "rd PCI_EXP_DEVCAP %#010x (%s)\n", reg32, __func__);
413	/* Calculate endpoint L0s acceptable latency */	430	/* Calculate endpoint L0s acceptable latency */
414	encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6;	431	encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6;
415	acceptable->l0s = calc_l0s_acceptable(encoding);	432	acceptable->l0s = calc_l0s_acceptable(encoding);
Lines 423-428 static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) Link Here
423		440
424	static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)	441	static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)
425	{	442	{
		443	dev_info(&pdev->dev, "wr PCI_EXP_LNKCTL clear %#010x set %#010x (%s)\n", PCI_EXP_LNKCTL_ASPMC, val, __func__);
426	pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL,	444	pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL,
427	PCI_EXP_LNKCTL_ASPMC, val);	445	PCI_EXP_LNKCTL_ASPMC, val);
428	}	446	}
Lines 503-508 static int pcie_aspm_sanity_check(struct pci_dev *pdev) Link Here
503	* RBER bit to determine if a function is 1.1 version device	521	* RBER bit to determine if a function is 1.1 version device
504	*/	522	*/
505	pcie_capability_read_dword(child, PCI_EXP_DEVCAP, &reg32);	523	pcie_capability_read_dword(child, PCI_EXP_DEVCAP, &reg32);
		524	dev_info(&child->dev, "rd PCI_EXP_DEVCAP %#010x (%s)\n", reg32, __func__);
506	if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) {	525	if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) {
507	dev_info(&child->dev, "disabling ASPM on pre-1.1 PCIe device. You can enable it with 'pcie_aspm=force'\n");	526	dev_info(&child->dev, "disabling ASPM on pre-1.1 PCIe device. You can enable it with 'pcie_aspm=force'\n");
508	return -EINVAL;	527	return -EINVAL;