Attachment #17260 for bug #11329




 * For VRD 10.0 and up, "VRD x.y Design Guide",
 * available at http://developer.intel.com/.
 *
 * AMD Athlon 64 and AMD Opteron Processors, AMD Publication 26094,
 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/26094.PDF
 * Table 74. VID Code Voltages
 * This corresponds to an arbitrary VRM code of 24 in the functions below.
 * These CPU models (K8 revision <= E) have 5 VID pins. See also:
 * Revision Guide for AMD Athlon 64 and AMD Opteron Processors, AMD Publication 25759,
 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf
 *
 * AMD NPT Family 0Fh Processors, AMD Publication 32559,
 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf
 * Table 71. VID Code Voltages
 * This corresponds to an arbitrary VRM code of 25 in the functions below.
 * These CPU models (K8 revision >= F) have 6 VID pins. See also:
 * Revision Guide for AMD NPT Family 0Fh Processors, AMD Publication 33610,
 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
 *
 * The 17 specification is in fact Intel Mobile Voltage Positioning -
 * (IMVP-II). You can find more information in the datasheet of Max1718

			return 0;
		return((1600000 - (val - 2) * 6250 + 500) / 1000);

	case 24:		/* Athlon64 & Opteron */
		val &= 0x1f;
		if (val == 0x1f)
			return 0;
				/* fall through */
	case 25:		/* AMD NPT 0Fh */
		val &= 0x3f;
		return (val < 32) ? 1550 - 25 * val
			: 775 - (25 * (val - 31)) / 2;


#ifdef CONFIG_X86

/*
 * The stepping parameter is highest acceptable stepping for current line.
 * The model match must be exact for 4-bit values. For model values 0x10
 * and above (extended model), all models below the parameter will match.
 */

static struct vrm_model vrm_models[] = {
	{X86_VENDOR_AMD, 0x6, ANY, ANY, 90},		/* Athlon Duron etc */
	{X86_VENDOR_AMD, 0xF, 0x3F, ANY, 24},		/* Athlon 64, Opteron */
	{X86_VENDOR_AMD, 0xF, ANY, ANY, 25},		/* NPT family 0Fh */
	{X86_VENDOR_INTEL, 0x6, 0x9, ANY, 13},		/* Pentium M (130 nm) */
	{X86_VENDOR_INTEL, 0x6, 0xB, ANY, 85},		/* Tualatin */
	{X86_VENDOR_INTEL, 0x6, 0xD, ANY, 13},		/* Pentium M (90 nm) */

		if (vrm_models[i].vendor==vendor)
			if ((vrm_models[i].eff_family==eff_family)
			 && ((vrm_models[i].eff_model==eff_model) ||
			     (vrm_models[i].eff_model >= 0x10 &&
			      eff_model <= vrm_models[i].eff_model) ||
			     (vrm_models[i].eff_model==ANY)) &&
			     (eff_stepping <= vrm_models[i].eff_stepping))
				return vrm_models[i].vrm_type;

Return to bug 11329

Lines 37-49 Link Here

(-)linux-2.6.27-rc3.orig/drivers/hwmon/hwmon-vid.c (-8 / +28 lines)
37	* For VRD 10.0 and up, "VRD x.y Design Guide",	37	* For VRD 10.0 and up, "VRD x.y Design Guide",
38	* available at http://developer.intel.com/.	38	* available at http://developer.intel.com/.
39	*	39	*
40	* AMD NPT 0Fh (Athlon64 & Opteron), AMD Publication 32559,	40	* AMD Athlon 64 and AMD Opteron Processors, AMD Publication 26094,
		41	* http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/26094.PDF
		42	* Table 74. VID Code Voltages
		43	* This corresponds to an arbitrary VRM code of 24 in the functions below.
		44	* These CPU models (K8 revision <= E) have 5 VID pins. See also:
		45	* Revision Guide for AMD Athlon 64 and AMD Opteron Processors, AMD Publication 25759,
		46	* http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf
		47	*
		48	* AMD NPT Family 0Fh Processors, AMD Publication 32559,
41	* http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf	49	* http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf
42	* Table 71. VID Code Voltages	50	* Table 71. VID Code Voltages
43	* AMD Opteron processors don't follow the Intel specifications.	51	* This corresponds to an arbitrary VRM code of 25 in the functions below.
44	* I'm going to "make up" 2.4 as the spec number for the Opterons.	52	* These CPU models (K8 revision >= F) have 6 VID pins. See also:
45	* No good reason just a mnemonic for the 24x Opteron processor	53	* Revision Guide for AMD NPT Family 0Fh Processors, AMD Publication 33610,
46	* series.	54	* http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
47	*	55	*
48	* The 17 specification is in fact Intel Mobile Voltage Positioning -	56	* The 17 specification is in fact Intel Mobile Voltage Positioning -
49	* (IMVP-II). You can find more information in the datasheet of Max1718	57	* (IMVP-II). You can find more information in the datasheet of Max1718
Lines 95-101 int vid_from_reg(int val, u8 vrm) Link Here
95	return 0;	103	return 0;
96	return((1600000 - (val - 2) * 6250 + 500) / 1000);	104	return((1600000 - (val - 2) * 6250 + 500) / 1000);
97		105
98	case 24: /* AMD NPT 0Fh (Athlon64 & Opteron) */	106	case 24: /* Athlon64 & Opteron */
		107	val &= 0x1f;
		108	if (val == 0x1f)
		109	return 0;
		110	/* fall through */
		111	case 25: /* AMD NPT 0Fh */
99	val &= 0x3f;	112	val &= 0x3f;
100	return (val < 32) ? 1550 - 25 * val	113	return (val < 32) ? 1550 - 25 * val
101	: 775 - (25 * (val - 31)) / 2;	114	: 775 - (25 * (val - 31)) / 2;
Lines 157-167 struct vrm_model { Link Here
157		170
158	#ifdef CONFIG_X86	171	#ifdef CONFIG_X86
159		172
160	/* the stepping parameter is highest acceptable stepping for current line */	173	/*
		174	* The stepping parameter is highest acceptable stepping for current line.
		175	* The model match must be exact for 4-bit values. For model values 0x10
		176	* and above (extended model), all models below the parameter will match.
		177	*/
161		178
162	static struct vrm_model vrm_models[] = {	179	static struct vrm_model vrm_models[] = {
163	{X86_VENDOR_AMD, 0x6, ANY, ANY, 90}, /* Athlon Duron etc */	180	{X86_VENDOR_AMD, 0x6, ANY, ANY, 90}, /* Athlon Duron etc */
164	{X86_VENDOR_AMD, 0xF, ANY, ANY, 24}, /* Athlon 64, Opteron and above VRM 24 */	181	{X86_VENDOR_AMD, 0xF, 0x3F, ANY, 24}, /* Athlon 64, Opteron */
		182	{X86_VENDOR_AMD, 0xF, ANY, ANY, 25}, /* NPT family 0Fh */
165	{X86_VENDOR_INTEL, 0x6, 0x9, ANY, 13}, /* Pentium M (130 nm) */	183	{X86_VENDOR_INTEL, 0x6, 0x9, ANY, 13}, /* Pentium M (130 nm) */
166	{X86_VENDOR_INTEL, 0x6, 0xB, ANY, 85}, /* Tualatin */	184	{X86_VENDOR_INTEL, 0x6, 0xB, ANY, 85}, /* Tualatin */
167	{X86_VENDOR_INTEL, 0x6, 0xD, ANY, 13}, /* Pentium M (90 nm) */	185	{X86_VENDOR_INTEL, 0x6, 0xD, ANY, 13}, /* Pentium M (90 nm) */
Lines 189-194 static u8 find_vrm(u8 eff_family, u8 eff Link Here
189	if (vrm_models[i].vendor==vendor)	207	if (vrm_models[i].vendor==vendor)
190	if ((vrm_models[i].eff_family==eff_family)	208	if ((vrm_models[i].eff_family==eff_family)
191	&& ((vrm_models[i].eff_model==eff_model) \|\|	209	&& ((vrm_models[i].eff_model==eff_model) \|\|
		210	(vrm_models[i].eff_model >= 0x10 &&
		211	eff_model <= vrm_models[i].eff_model) \|\|
192	(vrm_models[i].eff_model==ANY)) &&	212	(vrm_models[i].eff_model==ANY)) &&
193	(eff_stepping <= vrm_models[i].eff_stepping))	213	(eff_stepping <= vrm_models[i].eff_stepping))
194	return vrm_models[i].vrm_type;	214	return vrm_models[i].vrm_type;