Attachment #14455 for bug #9721

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	static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
	static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };

	sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
	reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
	/* Turn on/off phy power saving */
	if (onoff)

		reg1 |= coma_mode[port];

	sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
	sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
	sky2_pci_read32(hw, PCI_DEV_REG1);

	udelay(100);
}

	if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
		u16 pci_err;

		sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
		pci_err = sky2_pci_read16(hw, PCI_STATUS);
		if (net_ratelimit())
			dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",


		sky2_pci_write16(hw, PCI_STATUS,
				      pci_err | PCI_STATUS_ERROR_BITS);
		sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
	}

	if (status & Y2_IS_PCI_EXP) {
		/* PCI-Express uncorrectable Error occurred */
		u32 err;

		sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
		err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
		sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
			     0xfffffffful);

			dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);

		sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
		sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
	}

	if (status & Y2_HWE_L1_MASK)

	}

	sky2_power_on(hw);
	sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);

	for (i = 0; i < hw->ports; i++) {
		sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);

Return to bug 9721

Lines 621-626 static void sky2_phy_power(struct sky2_h Link Here

(-)a/drivers/net/sky2.c (-1 / +8 lines)
621	static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };	621	static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
622	static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };	622	static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
623		623
		624	sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
624	reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);	625	reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
625	/* Turn on/off phy power saving */	626	/* Turn on/off phy power saving */
626	if (onoff)	627	if (onoff)
Lines 632-638 static void sky2_phy_power(struct sky2_h Link Here
632	reg1 \|= coma_mode[port];	633	reg1 \|= coma_mode[port];
633		634
634	sky2_pci_write32(hw, PCI_DEV_REG1, reg1);	635	sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
635	reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);	636	sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
		637	sky2_pci_read32(hw, PCI_DEV_REG1);
636		638
637	udelay(100);	639	udelay(100);
638	}	640	}
Lines 2426-2431 static void sky2_hw_intr(struct sky2_hw Link Here
2426	if (status & (Y2_IS_MST_ERR \| Y2_IS_IRQ_STAT)) {	2428	if (status & (Y2_IS_MST_ERR \| Y2_IS_IRQ_STAT)) {
2427	u16 pci_err;	2429	u16 pci_err;
2428		2430
		2431	sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2429	pci_err = sky2_pci_read16(hw, PCI_STATUS);	2432	pci_err = sky2_pci_read16(hw, PCI_STATUS);
2430	if (net_ratelimit())	2433	if (net_ratelimit())
2431	dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",	2434	dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
Lines 2433-2444 static void sky2_hw_intr(struct sky2_hw Link Here
2433		2436
2434	sky2_pci_write16(hw, PCI_STATUS,	2437	sky2_pci_write16(hw, PCI_STATUS,
2435	pci_err \| PCI_STATUS_ERROR_BITS);	2438	pci_err \| PCI_STATUS_ERROR_BITS);
		2439	sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2436	}	2440	}
2437		2441
2438	if (status & Y2_IS_PCI_EXP) {	2442	if (status & Y2_IS_PCI_EXP) {
2439	/* PCI-Express uncorrectable Error occurred */	2443	/* PCI-Express uncorrectable Error occurred */
2440	u32 err;	2444	u32 err;
2441		2445
		2446	sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2442	err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);	2447	err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2443	sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,	2448	sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2444	0xfffffffful);	2449	0xfffffffful);
Lines 2446-2451 static void sky2_hw_intr(struct sky2_hw Link Here
2446	dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);	2451	dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2447		2452
2448	sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);	2453	sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
		2454	sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2449	}	2455	}
2450		2456
2451	if (status & Y2_HWE_L1_MASK)	2457	if (status & Y2_HWE_L1_MASK)
Lines 2811-2816 static void sky2_reset(struct sky2_hw *h Link Here
2811	}	2817	}
2812		2818
2813	sky2_power_on(hw);	2819	sky2_power_on(hw);
		2820	sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2814		2821
2815	for (i = 0; i < hw->ports; i++) {	2822	for (i = 0; i < hw->ports; i++) {
2816	sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);	2823	sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);