Lines 636-656
int pciehp_reset_slot(struct slot *slot, int probe)
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|
636 |
if (probe) |
636 |
if (probe) |
637 |
return 0; |
637 |
return 0; |
638 |
|
638 |
|
639 |
if (HP_SUPR_RM(ctrl)) { |
639 |
pcie_write_cmd(ctrl, 0, PCI_EXP_SLTCTL_PDCE); |
640 |
pcie_write_cmd(ctrl, 0, PCI_EXP_SLTCTL_PDCE); |
640 |
if (pciehp_poll_mode) |
641 |
if (pciehp_poll_mode) |
641 |
del_timer_sync(&ctrl->poll_timer); |
642 |
del_timer_sync(&ctrl->poll_timer); |
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|
643 |
} |
644 |
|
642 |
|
645 |
pci_reset_bridge_secondary_bus(ctrl->pcie->port); |
643 |
pci_reset_bridge_secondary_bus(ctrl->pcie->port); |
646 |
|
644 |
|
647 |
if (HP_SUPR_RM(ctrl)) { |
645 |
pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_PDC); |
648 |
pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, |
646 |
pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PDCE, PCI_EXP_SLTCTL_PDCE); |
649 |
PCI_EXP_SLTSTA_PDC); |
647 |
if (pciehp_poll_mode) |
650 |
pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PDCE, PCI_EXP_SLTCTL_PDCE); |
648 |
int_poll_timeout(ctrl->poll_timer.data); |
651 |
if (pciehp_poll_mode) |
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|
652 |
int_poll_timeout(ctrl->poll_timer.data); |
653 |
} |
654 |
|
649 |
|
655 |
return 0; |
650 |
return 0; |
656 |
} |
651 |
} |
657 |
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