Lines 158-163
static const u8 cckswing_table_ch14[CCK_
Link Here
|
158 |
{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} |
158 |
{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} |
159 |
}; |
159 |
}; |
160 |
|
160 |
|
|
|
161 |
static u32 power_index_reg[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a}; |
162 |
|
163 |
void dm_restorepowerindex(struct ieee80211_hw *hw) |
164 |
{ |
165 |
struct rtl_priv *rtlpriv = rtl_priv(hw); |
166 |
u8 index; |
167 |
|
168 |
for (index = 0; index < 6; index++) |
169 |
rtl_write_byte(rtlpriv, power_index_reg[index], |
170 |
rtlpriv->dm.powerindex_backup[index]); |
171 |
} |
172 |
EXPORT_SYMBOL_GPL(dm_restorepowerindex); |
173 |
|
174 |
void dm_writepowerindex(struct ieee80211_hw *hw, u8 value) |
175 |
{ |
176 |
struct rtl_priv *rtlpriv = rtl_priv(hw); |
177 |
u8 index; |
178 |
|
179 |
for (index = 0; index < 6; index++) |
180 |
rtl_write_byte(rtlpriv, power_index_reg[index], value); |
181 |
} |
182 |
EXPORT_SYMBOL_GPL(dm_writepowerindex); |
183 |
|
184 |
void dm_savepowerindex(struct ieee80211_hw *hw) |
185 |
{ |
186 |
struct rtl_priv *rtlpriv = rtl_priv(hw); |
187 |
u8 index; |
188 |
u8 tmp; |
189 |
|
190 |
for (index = 0; index < 6; index++) { |
191 |
tmp = rtl_read_byte(rtlpriv, power_index_reg[index]); |
192 |
rtlpriv->dm.powerindex_backup[index] = tmp; |
193 |
} |
194 |
} |
195 |
EXPORT_SYMBOL_GPL(dm_savepowerindex); |
196 |
|
161 |
static void rtl92c_dm_diginit(struct ieee80211_hw *hw) |
197 |
static void rtl92c_dm_diginit(struct ieee80211_hw *hw) |
162 |
{ |
198 |
{ |
163 |
struct rtl_priv *rtlpriv = rtl_priv(hw); |
199 |
struct rtl_priv *rtlpriv = rtl_priv(hw); |
Lines 180-186
static void rtl92c_dm_diginit(struct iee
Link Here
|
180 |
dm_digtable->back_range_max = DM_DIG_BACKOFF_MAX; |
216 |
dm_digtable->back_range_max = DM_DIG_BACKOFF_MAX; |
181 |
dm_digtable->back_range_min = DM_DIG_BACKOFF_MIN; |
217 |
dm_digtable->back_range_min = DM_DIG_BACKOFF_MIN; |
182 |
dm_digtable->pre_cck_pd_state = CCK_PD_STAGE_MAX; |
218 |
dm_digtable->pre_cck_pd_state = CCK_PD_STAGE_MAX; |
183 |
dm_digtable->cur_cck_pd_state = CCK_PD_STAGE_MAX; |
219 |
dm_digtable->cur_cck_pd_state = CCK_PD_STAGE_LowRssi; |
|
|
220 |
|
221 |
dm_digtable->forbidden_igi = DM_DIG_MIN; |
222 |
dm_digtable->large_fa_hit = 0; |
223 |
dm_digtable->recover_cnt = 0; |
224 |
dm_digtable->dig_dynamic_min = 0x25; |
184 |
} |
225 |
} |
185 |
|
226 |
|
186 |
static u8 rtl92c_dm_initial_gain_min_pwdb(struct ieee80211_hw *hw) |
227 |
static u8 rtl92c_dm_initial_gain_min_pwdb(struct ieee80211_hw *hw) |
Lines 206-212
static u8 rtl92c_dm_initial_gain_min_pwd
Link Here
|
206 |
rssi_val_min = rtlpriv->dm.entry_min_undec_sm_pwdb; |
247 |
rssi_val_min = rtlpriv->dm.entry_min_undec_sm_pwdb; |
207 |
} |
248 |
} |
208 |
|
249 |
|
209 |
return (u8) rssi_val_min; |
250 |
if (rssi_val_min > 100) |
|
|
251 |
rssi_val_min = 100; |
252 |
return (u8)rssi_val_min; |
210 |
} |
253 |
} |
211 |
|
254 |
|
212 |
static void rtl92c_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw) |
255 |
static void rtl92c_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw) |
Lines 224-232
static void rtl92c_dm_false_alarm_counte
Link Here
|
224 |
|
267 |
|
225 |
ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD); |
268 |
ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD); |
226 |
falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff); |
269 |
falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff); |
|
|
270 |
|
271 |
ret_value = rtl_get_bbreg(hw, ROFDM0_FRAMESYNC, MASKDWORD); |
272 |
falsealm_cnt->cnt_fast_fsync_fail = (ret_value & 0xffff); |
273 |
falsealm_cnt->cnt_sb_search_fail = ((ret_value & 0xffff0000) >> 16); |
274 |
|
227 |
falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail + |
275 |
falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail + |
228 |
falsealm_cnt->cnt_rate_illegal + |
276 |
falsealm_cnt->cnt_rate_illegal + |
229 |
falsealm_cnt->cnt_crc8_fail + falsealm_cnt->cnt_mcs_fail; |
277 |
falsealm_cnt->cnt_crc8_fail + |
|
|
278 |
falsealm_cnt->cnt_mcs_fail + |
279 |
falsealm_cnt->cnt_fast_fsync_fail + |
280 |
falsealm_cnt->cnt_sb_search_fail; |
230 |
|
281 |
|
231 |
rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(14), 1); |
282 |
rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(14), 1); |
232 |
ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, MASKBYTE0); |
283 |
ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, MASKBYTE0); |
Lines 271-282
static void rtl92c_dm_ctrl_initgain_by_f
Link Here
|
271 |
value_igi++; |
322 |
value_igi++; |
272 |
else if (rtlpriv->falsealm_cnt.cnt_all >= DM_DIG_FA_TH2) |
323 |
else if (rtlpriv->falsealm_cnt.cnt_all >= DM_DIG_FA_TH2) |
273 |
value_igi += 2; |
324 |
value_igi += 2; |
|
|
325 |
|
274 |
if (value_igi > DM_DIG_FA_UPPER) |
326 |
if (value_igi > DM_DIG_FA_UPPER) |
275 |
value_igi = DM_DIG_FA_UPPER; |
327 |
value_igi = DM_DIG_FA_UPPER; |
276 |
else if (value_igi < DM_DIG_FA_LOWER) |
328 |
else if (value_igi < DM_DIG_FA_LOWER) |
277 |
value_igi = DM_DIG_FA_LOWER; |
329 |
value_igi = DM_DIG_FA_LOWER; |
|
|
330 |
|
278 |
if (rtlpriv->falsealm_cnt.cnt_all > 10000) |
331 |
if (rtlpriv->falsealm_cnt.cnt_all > 10000) |
279 |
value_igi = 0x32; |
332 |
value_igi = DM_DIG_FA_UPPER; |
280 |
|
333 |
|
281 |
dm_digtable->cur_igvalue = value_igi; |
334 |
dm_digtable->cur_igvalue = value_igi; |
282 |
rtl92c_dm_write_dig(hw); |
335 |
rtl92c_dm_write_dig(hw); |
Lines 286-317
static void rtl92c_dm_ctrl_initgain_by_r
Link Here
|
286 |
{ |
339 |
{ |
287 |
struct rtl_priv *rtlpriv = rtl_priv(hw); |
340 |
struct rtl_priv *rtlpriv = rtl_priv(hw); |
288 |
struct dig_t *digtable = &rtlpriv->dm_digtable; |
341 |
struct dig_t *digtable = &rtlpriv->dm_digtable; |
|
|
342 |
u32 isbt; |
289 |
|
343 |
|
290 |
if (rtlpriv->falsealm_cnt.cnt_all > digtable->fa_highthresh) { |
344 |
/* modify DIG lower bound, deal with abnorally large false alarm */ |
291 |
if ((digtable->back_val - 2) < digtable->back_range_min) |
345 |
if (rtlpriv->falsealm_cnt.cnt_all > 10000) { |
292 |
digtable->back_val = digtable->back_range_min; |
346 |
digtable->large_fa_hit++; |
293 |
else |
347 |
if (digtable->forbidden_igi < digtable->cur_igvalue) { |
294 |
digtable->back_val -= 2; |
348 |
digtable->forbidden_igi = digtable->cur_igvalue; |
295 |
} else if (rtlpriv->falsealm_cnt.cnt_all < digtable->fa_lowthresh) { |
349 |
digtable->large_fa_hit = 1; |
296 |
if ((digtable->back_val + 2) > digtable->back_range_max) |
350 |
} |
297 |
digtable->back_val = digtable->back_range_max; |
351 |
|
298 |
else |
352 |
if (digtable->large_fa_hit >= 3) { |
299 |
digtable->back_val += 2; |
353 |
if ((digtable->forbidden_igi + 1) > |
|
|
354 |
digtable->rx_gain_max) |
355 |
digtable->rx_gain_min = digtable->rx_gain_max; |
356 |
else |
357 |
digtable->rx_gain_min = (digtable->forbidden_igi + 1); |
358 |
digtable->recover_cnt = 3600; /* 3600=2hr */ |
359 |
} |
360 |
} else { |
361 |
/* Recovery mechanism for IGI lower bound */ |
362 |
if (digtable->recover_cnt != 0) { |
363 |
digtable->recover_cnt--; |
364 |
} else { |
365 |
if (digtable->large_fa_hit == 0) { |
366 |
if ((digtable->forbidden_igi-1) < DM_DIG_MIN) { |
367 |
digtable->forbidden_igi = DM_DIG_MIN; |
368 |
digtable->rx_gain_min = DM_DIG_MIN; |
369 |
} else { |
370 |
digtable->forbidden_igi--; |
371 |
digtable->rx_gain_min = digtable->forbidden_igi + 1; |
372 |
} |
373 |
} else if (digtable->large_fa_hit == 3) { |
374 |
digtable->large_fa_hit = 0; |
375 |
} |
376 |
} |
300 |
} |
377 |
} |
|
|
378 |
if (rtlpriv->falsealm_cnt.cnt_all < 250) { |
379 |
isbt = rtl_read_byte(rtlpriv, 0x4fd) & 0x01; |
301 |
|
380 |
|
302 |
if ((digtable->rssi_val_min + 10 - digtable->back_val) > |
381 |
if (!isbt) { |
303 |
digtable->rx_gain_max) |
382 |
if (rtlpriv->falsealm_cnt.cnt_all > |
|
|
383 |
digtable->fa_lowthresh) { |
384 |
if ((digtable->back_val - 2) < |
385 |
digtable->back_range_min) |
386 |
digtable->back_val = digtable->back_range_min; |
387 |
else |
388 |
digtable->back_val -= 2; |
389 |
} else if (rtlpriv->falsealm_cnt.cnt_all < |
390 |
digtable->fa_lowthresh) { |
391 |
if ((digtable->back_val + 2) > |
392 |
digtable->back_range_max) |
393 |
digtable->back_val = digtable->back_range_max; |
394 |
else |
395 |
digtable->back_val += 2; |
396 |
} |
397 |
} else { |
398 |
digtable->back_val = DM_DIG_BACKOFF_DEFAULT; |
399 |
} |
400 |
} else { |
401 |
/* Adjust initial gain by false alarm */ |
402 |
if (rtlpriv->falsealm_cnt.cnt_all > 1000) |
403 |
digtable->cur_igvalue = digtable->pre_igvalue + 2; |
404 |
else if (rtlpriv->falsealm_cnt.cnt_all > 750) |
405 |
digtable->cur_igvalue = digtable->pre_igvalue + 1; |
406 |
else if (rtlpriv->falsealm_cnt.cnt_all < 500) |
407 |
digtable->cur_igvalue = digtable->pre_igvalue - 1; |
408 |
} |
409 |
|
410 |
/* Check initial gain by upper/lower bound */ |
411 |
if (digtable->cur_igvalue > digtable->rx_gain_max) |
304 |
digtable->cur_igvalue = digtable->rx_gain_max; |
412 |
digtable->cur_igvalue = digtable->rx_gain_max; |
305 |
else if ((digtable->rssi_val_min + 10 - |
|
|
306 |
digtable->back_val) < digtable->rx_gain_min) |
307 |
digtable->cur_igvalue = digtable->rx_gain_min; |
308 |
else |
309 |
digtable->cur_igvalue = digtable->rssi_val_min + 10 - |
310 |
digtable->back_val; |
311 |
|
413 |
|
312 |
RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, |
414 |
if (digtable->cur_igvalue < digtable->rx_gain_min) |
313 |
"rssi_val_min = %x back_val %x\n", |
415 |
digtable->cur_igvalue = digtable->rx_gain_min; |
314 |
digtable->rssi_val_min, digtable->back_val); |
|
|
315 |
|
416 |
|
316 |
rtl92c_dm_write_dig(hw); |
417 |
rtl92c_dm_write_dig(hw); |
317 |
} |
418 |
} |
Lines 329-335
static void rtl92c_dm_initial_gain_multi
Link Here
|
329 |
multi_sta = true; |
430 |
multi_sta = true; |
330 |
|
431 |
|
331 |
if (!multi_sta || |
432 |
if (!multi_sta || |
332 |
dm_digtable->cursta_cstate != DIG_STA_DISCONNECT) { |
433 |
dm_digtable->cursta_cstate == DIG_STA_DISCONNECT) { |
333 |
initialized = false; |
434 |
initialized = false; |
334 |
dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX; |
435 |
dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX; |
335 |
return; |
436 |
return; |
Lines 375-381
static void rtl92c_dm_initial_gain_sta(s
Link Here
|
375 |
RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, |
476 |
RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, |
376 |
"presta_cstate = %x, cursta_cstate = %x\n", |
477 |
"presta_cstate = %x, cursta_cstate = %x\n", |
377 |
dm_digtable->presta_cstate, dm_digtable->cursta_cstate); |
478 |
dm_digtable->presta_cstate, dm_digtable->cursta_cstate); |
378 |
|
|
|
379 |
if (dm_digtable->presta_cstate == dm_digtable->cursta_cstate || |
479 |
if (dm_digtable->presta_cstate == dm_digtable->cursta_cstate || |
380 |
dm_digtable->cursta_cstate == DIG_STA_BEFORE_CONNECT || |
480 |
dm_digtable->cursta_cstate == DIG_STA_BEFORE_CONNECT || |
381 |
dm_digtable->cursta_cstate == DIG_STA_CONNECT) { |
481 |
dm_digtable->cursta_cstate == DIG_STA_CONNECT) { |
Lines 383-388
static void rtl92c_dm_initial_gain_sta(s
Link Here
|
383 |
if (dm_digtable->cursta_cstate != DIG_STA_DISCONNECT) { |
483 |
if (dm_digtable->cursta_cstate != DIG_STA_DISCONNECT) { |
384 |
dm_digtable->rssi_val_min = |
484 |
dm_digtable->rssi_val_min = |
385 |
rtl92c_dm_initial_gain_min_pwdb(hw); |
485 |
rtl92c_dm_initial_gain_min_pwdb(hw); |
|
|
486 |
if (dm_digtable->rssi_val_min > 100) |
487 |
dm_digtable->rssi_val_min = 100; |
386 |
rtl92c_dm_ctrl_initgain_by_rssi(hw); |
488 |
rtl92c_dm_ctrl_initgain_by_rssi(hw); |
387 |
} |
489 |
} |
388 |
} else { |
490 |
} else { |
Lines 398-408
static void rtl92c_dm_initial_gain_sta(s
Link Here
|
398 |
static void rtl92c_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw) |
500 |
static void rtl92c_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw) |
399 |
{ |
501 |
{ |
400 |
struct rtl_priv *rtlpriv = rtl_priv(hw); |
502 |
struct rtl_priv *rtlpriv = rtl_priv(hw); |
401 |
struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); |
|
|
402 |
struct dig_t *dm_digtable = &rtlpriv->dm_digtable; |
503 |
struct dig_t *dm_digtable = &rtlpriv->dm_digtable; |
403 |
|
504 |
|
404 |
if (dm_digtable->cursta_cstate == DIG_STA_CONNECT) { |
505 |
if (dm_digtable->cursta_cstate == DIG_STA_CONNECT) { |
405 |
dm_digtable->rssi_val_min = rtl92c_dm_initial_gain_min_pwdb(hw); |
506 |
dm_digtable->rssi_val_min = rtl92c_dm_initial_gain_min_pwdb(hw); |
|
|
507 |
if (dm_digtable->rssi_val_min > 100) |
508 |
dm_digtable->rssi_val_min = 100; |
406 |
|
509 |
|
407 |
if (dm_digtable->pre_cck_pd_state == CCK_PD_STAGE_LowRssi) { |
510 |
if (dm_digtable->pre_cck_pd_state == CCK_PD_STAGE_LowRssi) { |
408 |
if (dm_digtable->rssi_val_min <= 25) |
511 |
if (dm_digtable->rssi_val_min <= 25) |
Lines 424-471
static void rtl92c_dm_cck_packet_detecti
Link Here
|
424 |
} |
527 |
} |
425 |
|
528 |
|
426 |
if (dm_digtable->pre_cck_pd_state != dm_digtable->cur_cck_pd_state) { |
529 |
if (dm_digtable->pre_cck_pd_state != dm_digtable->cur_cck_pd_state) { |
427 |
if (dm_digtable->cur_cck_pd_state == CCK_PD_STAGE_LowRssi) { |
530 |
if ((dm_digtable->cur_cck_pd_state == CCK_PD_STAGE_LowRssi) || |
428 |
if (rtlpriv->falsealm_cnt.cnt_cck_fail > 800) |
531 |
(dm_digtable->cur_cck_pd_state == CCK_PD_STAGE_MAX)) |
429 |
dm_digtable->cur_cck_fa_state = |
532 |
rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x83); |
430 |
CCK_FA_STAGE_High; |
533 |
else |
431 |
else |
|
|
432 |
dm_digtable->cur_cck_fa_state = CCK_FA_STAGE_Low; |
433 |
|
434 |
if (dm_digtable->pre_cck_fa_state != |
435 |
dm_digtable->cur_cck_fa_state) { |
436 |
if (dm_digtable->cur_cck_fa_state == |
437 |
CCK_FA_STAGE_Low) |
438 |
rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, |
439 |
0x83); |
440 |
else |
441 |
rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, |
442 |
0xcd); |
443 |
|
444 |
dm_digtable->pre_cck_fa_state = |
445 |
dm_digtable->cur_cck_fa_state; |
446 |
} |
447 |
|
448 |
rtl_set_bbreg(hw, RCCK0_SYSTEM, MASKBYTE1, 0x40); |
449 |
|
450 |
if (IS_92C_SERIAL(rtlhal->version)) |
451 |
rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, |
452 |
MASKBYTE2, 0xd7); |
453 |
} else { |
454 |
rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd); |
534 |
rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd); |
455 |
rtl_set_bbreg(hw, RCCK0_SYSTEM, MASKBYTE1, 0x47); |
|
|
456 |
|
535 |
|
457 |
if (IS_92C_SERIAL(rtlhal->version)) |
|
|
458 |
rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, |
459 |
MASKBYTE2, 0xd3); |
460 |
} |
461 |
dm_digtable->pre_cck_pd_state = dm_digtable->cur_cck_pd_state; |
536 |
dm_digtable->pre_cck_pd_state = dm_digtable->cur_cck_pd_state; |
462 |
} |
537 |
} |
463 |
|
|
|
464 |
RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, "CCKPDStage=%x\n", |
465 |
dm_digtable->cur_cck_pd_state); |
466 |
|
467 |
RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, "is92C=%x\n", |
468 |
IS_92C_SERIAL(rtlhal->version)); |
469 |
} |
538 |
} |
470 |
|
539 |
|
471 |
static void rtl92c_dm_ctrl_initgain_by_twoport(struct ieee80211_hw *hw) |
540 |
static void rtl92c_dm_ctrl_initgain_by_twoport(struct ieee80211_hw *hw) |
Lines 482-487
static void rtl92c_dm_ctrl_initgain_by_t
Link Here
|
482 |
else |
551 |
else |
483 |
dm_digtable->cursta_cstate = DIG_STA_DISCONNECT; |
552 |
dm_digtable->cursta_cstate = DIG_STA_DISCONNECT; |
484 |
|
553 |
|
|
|
554 |
dm_digtable->curmultista_cstate = DIG_MULTISTA_DISCONNECT; |
555 |
|
485 |
rtl92c_dm_initial_gain_sta(hw); |
556 |
rtl92c_dm_initial_gain_sta(hw); |
486 |
rtl92c_dm_initial_gain_multi_sta(hw); |
557 |
rtl92c_dm_initial_gain_multi_sta(hw); |
487 |
rtl92c_dm_cck_packet_detection_thresh(hw); |
558 |
rtl92c_dm_cck_packet_detection_thresh(hw); |
Lines 493-515
static void rtl92c_dm_ctrl_initgain_by_t
Link Here
|
493 |
static void rtl92c_dm_dig(struct ieee80211_hw *hw) |
564 |
static void rtl92c_dm_dig(struct ieee80211_hw *hw) |
494 |
{ |
565 |
{ |
495 |
struct rtl_priv *rtlpriv = rtl_priv(hw); |
566 |
struct rtl_priv *rtlpriv = rtl_priv(hw); |
496 |
struct dig_t *dm_digtable = &rtlpriv->dm_digtable; |
|
|
497 |
|
567 |
|
498 |
if (rtlpriv->dm.dm_initialgain_enable == false) |
568 |
if (rtlpriv->dm.dm_initialgain_enable == false) |
499 |
return; |
569 |
return; |
500 |
if (dm_digtable->dig_enable_flag == false) |
570 |
if (!rtlpriv->dm.dm_flag & DYNAMIC_FUNC_DIG) |
501 |
return; |
571 |
return; |
502 |
|
572 |
|
503 |
rtl92c_dm_ctrl_initgain_by_twoport(hw); |
573 |
rtl92c_dm_ctrl_initgain_by_twoport(hw); |
504 |
|
|
|
505 |
} |
574 |
} |
506 |
|
575 |
|
507 |
static void rtl92c_dm_init_dynamic_txpower(struct ieee80211_hw *hw) |
576 |
static void rtl92c_dm_init_dynamic_txpower(struct ieee80211_hw *hw) |
508 |
{ |
577 |
{ |
509 |
struct rtl_priv *rtlpriv = rtl_priv(hw); |
578 |
struct rtl_priv *rtlpriv = rtl_priv(hw); |
510 |
|
579 |
|
511 |
rtlpriv->dm.dynamic_txpower_enable = false; |
580 |
if (rtlpriv->rtlhal.interface == INTF_USB && |
512 |
|
581 |
rtlpriv->rtlhal.board_type & 0x1) { |
|
|
582 |
dm_savepowerindex(hw); |
583 |
rtlpriv->dm.dynamic_txpower_enable = true; |
584 |
} else { |
585 |
rtlpriv->dm.dynamic_txpower_enable = false; |
586 |
} |
513 |
rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL; |
587 |
rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL; |
514 |
rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL; |
588 |
rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL; |
515 |
} |
589 |
} |
Lines 524-532
void rtl92c_dm_write_dig(struct ieee8021
Link Here
|
524 |
dm_digtable->cur_igvalue, dm_digtable->pre_igvalue, |
598 |
dm_digtable->cur_igvalue, dm_digtable->pre_igvalue, |
525 |
dm_digtable->back_val); |
599 |
dm_digtable->back_val); |
526 |
|
600 |
|
527 |
dm_digtable->cur_igvalue += 2; |
601 |
if (rtlpriv->rtlhal.interface == INTF_USB && |
528 |
if (dm_digtable->cur_igvalue > 0x3f) |
602 |
!dm_digtable->dig_enable_flag) { |
529 |
dm_digtable->cur_igvalue = 0x3f; |
603 |
dm_digtable->pre_igvalue = 0x17; |
|
|
604 |
return; |
605 |
} |
606 |
dm_digtable->cur_igvalue -= 1; |
607 |
if (dm_digtable->cur_igvalue < DM_DIG_MIN) |
608 |
dm_digtable->cur_igvalue = DM_DIG_MIN; |
530 |
|
609 |
|
531 |
if (dm_digtable->pre_igvalue != dm_digtable->cur_igvalue) { |
610 |
if (dm_digtable->pre_igvalue != dm_digtable->cur_igvalue) { |
532 |
rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f, |
611 |
rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f, |
Lines 536-569
void rtl92c_dm_write_dig(struct ieee8021
Link Here
|
536 |
|
615 |
|
537 |
dm_digtable->pre_igvalue = dm_digtable->cur_igvalue; |
616 |
dm_digtable->pre_igvalue = dm_digtable->cur_igvalue; |
538 |
} |
617 |
} |
|
|
618 |
RT_TRACE(rtlpriv, COMP_DIG, DBG_WARNING, |
619 |
"dig values 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", |
620 |
dm_digtable->cur_igvalue, dm_digtable->pre_igvalue, |
621 |
dm_digtable->rssi_val_min, dm_digtable->back_val, |
622 |
dm_digtable->rx_gain_max, dm_digtable->rx_gain_min, |
623 |
dm_digtable->large_fa_hit, dm_digtable->forbidden_igi); |
539 |
} |
624 |
} |
540 |
EXPORT_SYMBOL(rtl92c_dm_write_dig); |
625 |
EXPORT_SYMBOL(rtl92c_dm_write_dig); |
541 |
|
626 |
|
542 |
static void rtl92c_dm_pwdb_monitor(struct ieee80211_hw *hw) |
627 |
static void rtl92c_dm_pwdb_monitor(struct ieee80211_hw *hw) |
543 |
{ |
628 |
{ |
544 |
struct rtl_priv *rtlpriv = rtl_priv(hw); |
629 |
struct rtl_priv *rtlpriv = rtl_priv(hw); |
|
|
630 |
struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); |
545 |
long tmpentry_max_pwdb = 0, tmpentry_min_pwdb = 0xff; |
631 |
long tmpentry_max_pwdb = 0, tmpentry_min_pwdb = 0xff; |
546 |
|
632 |
|
547 |
u8 h2c_parameter[3] = { 0 }; |
633 |
if (mac->link_state != MAC80211_LINKED) |
|
|
634 |
return; |
548 |
|
635 |
|
549 |
return; |
636 |
if (mac->opmode == NL80211_IFTYPE_ADHOC || |
|
|
637 |
mac->opmode == NL80211_IFTYPE_AP) { |
638 |
/* TODO: Handle ADHOC and AP Mode */ |
639 |
} |
550 |
|
640 |
|
551 |
if (tmpentry_max_pwdb != 0) { |
641 |
if (tmpentry_max_pwdb != 0) |
552 |
rtlpriv->dm.entry_max_undec_sm_pwdb = tmpentry_max_pwdb; |
642 |
rtlpriv->dm.entry_max_undec_sm_pwdb = tmpentry_max_pwdb; |
553 |
} else { |
643 |
else |
554 |
rtlpriv->dm.entry_max_undec_sm_pwdb = 0; |
644 |
rtlpriv->dm.entry_max_undec_sm_pwdb = 0; |
555 |
} |
|
|
556 |
|
645 |
|
557 |
if (tmpentry_min_pwdb != 0xff) { |
646 |
if (tmpentry_min_pwdb != 0xff) |
558 |
rtlpriv->dm.entry_min_undec_sm_pwdb = tmpentry_min_pwdb; |
647 |
rtlpriv->dm.entry_min_undec_sm_pwdb = tmpentry_min_pwdb; |
559 |
} else { |
648 |
else |
560 |
rtlpriv->dm.entry_min_undec_sm_pwdb = 0; |
649 |
rtlpriv->dm.entry_min_undec_sm_pwdb = 0; |
561 |
} |
|
|
562 |
|
650 |
|
563 |
h2c_parameter[2] = (u8) (rtlpriv->dm.undec_sm_pwdb & 0xFF); |
651 |
/* TODO: |
564 |
h2c_parameter[0] = 0; |
652 |
* if (mac->opmode == NL80211_IFTYPE_STATION) { |
565 |
|
653 |
* if (rtlpriv->rtlhal.fw_ready) { |
566 |
rtl92c_fill_h2c_cmd(hw, H2C_RSSI_REPORT, 3, h2c_parameter); |
654 |
* u32 param = (u32)(rtlpriv->dm.undec_sm_pwdb << 16); |
|
|
655 |
* rtl8192c_set_rssi_cmd(hw, param); |
656 |
* } |
657 |
* } |
658 |
*/ |
567 |
} |
659 |
} |
568 |
|
660 |
|
569 |
void rtl92c_dm_init_edca_turbo(struct ieee80211_hw *hw) |
661 |
void rtl92c_dm_init_edca_turbo(struct ieee80211_hw *hw) |
Lines 673-679
static void rtl92c_dm_txpower_tracking_c
Link Here
|
673 |
s8 cck_index = 0; |
765 |
s8 cck_index = 0; |
674 |
int i; |
766 |
int i; |
675 |
bool is2t = IS_92C_SERIAL(rtlhal->version); |
767 |
bool is2t = IS_92C_SERIAL(rtlhal->version); |
676 |
s8 txpwr_level[2] = {0, 0}; |
768 |
s8 txpwr_level[3] = {0, 0, 0}; |
677 |
u8 ofdm_min_index = 6, rf; |
769 |
u8 ofdm_min_index = 6, rf; |
678 |
|
770 |
|
679 |
rtlpriv->dm.txpower_trackinginit = true; |
771 |
rtlpriv->dm.txpower_trackinginit = true; |
Lines 773-778
static void rtl92c_dm_txpower_tracking_c
Link Here
|
773 |
rtlpriv->dm.ofdm_index[i] = ofdm_index_old[i]; |
865 |
rtlpriv->dm.ofdm_index[i] = ofdm_index_old[i]; |
774 |
rtlpriv->dm.cck_index = cck_index_old; |
866 |
rtlpriv->dm.cck_index = cck_index_old; |
775 |
} |
867 |
} |
|
|
868 |
/* Handle USB High PA boards */ |
776 |
|
869 |
|
777 |
delta = (thermalvalue > rtlpriv->dm.thermalvalue) ? |
870 |
delta = (thermalvalue > rtlpriv->dm.thermalvalue) ? |
778 |
(thermalvalue - rtlpriv->dm.thermalvalue) : |
871 |
(thermalvalue - rtlpriv->dm.thermalvalue) : |
Lines 1163-1184
void rtl92c_dm_rf_saving(struct ieee8021
Link Here
|
1163 |
{ |
1256 |
{ |
1164 |
struct rtl_priv *rtlpriv = rtl_priv(hw); |
1257 |
struct rtl_priv *rtlpriv = rtl_priv(hw); |
1165 |
struct ps_t *dm_pstable = &rtlpriv->dm_pstable; |
1258 |
struct ps_t *dm_pstable = &rtlpriv->dm_pstable; |
1166 |
static u8 initialize; |
|
|
1167 |
static u32 reg_874, reg_c70, reg_85c, reg_a74; |
1168 |
|
1259 |
|
1169 |
if (initialize == 0) { |
1260 |
if (!rtlpriv->reg_init) { |
1170 |
reg_874 = (rtl_get_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, |
1261 |
rtlpriv->reg_874 = (rtl_get_bbreg(hw, |
1171 |
MASKDWORD) & 0x1CC000) >> 14; |
1262 |
RFPGA0_XCD_RFINTERFACESW, |
|
|
1263 |
MASKDWORD) & 0x1CC000) >> 14; |
1172 |
|
1264 |
|
1173 |
reg_c70 = (rtl_get_bbreg(hw, ROFDM0_AGCPARAMETER1, |
1265 |
rtlpriv->reg_c70 = (rtl_get_bbreg(hw, ROFDM0_AGCPARAMETER1, |
1174 |
MASKDWORD) & BIT(3)) >> 3; |
1266 |
MASKDWORD) & BIT(3)) >> 3; |
1175 |
|
1267 |
|
1176 |
reg_85c = (rtl_get_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL, |
1268 |
rtlpriv->reg_85c = (rtl_get_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL, |
1177 |
MASKDWORD) & 0xFF000000) >> 24; |
1269 |
MASKDWORD) & 0xFF000000) >> 24; |
1178 |
|
1270 |
|
1179 |
reg_a74 = (rtl_get_bbreg(hw, 0xa74, MASKDWORD) & 0xF000) >> 12; |
1271 |
rtlpriv->reg_a74 = (rtl_get_bbreg(hw, 0xa74, MASKDWORD) & |
|
|
1272 |
0xF000) >> 12; |
1180 |
|
1273 |
|
1181 |
initialize = 1; |
1274 |
rtlpriv->reg_init = true; |
1182 |
} |
1275 |
} |
1183 |
|
1276 |
|
1184 |
if (!bforce_in_normal) { |
1277 |
if (!bforce_in_normal) { |
Lines 1215-1226
void rtl92c_dm_rf_saving(struct ieee8021
Link Here
|
1215 |
rtl_set_bbreg(hw, 0x818, BIT(28), 0x1); |
1308 |
rtl_set_bbreg(hw, 0x818, BIT(28), 0x1); |
1216 |
} else { |
1309 |
} else { |
1217 |
rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, |
1310 |
rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, |
1218 |
0x1CC000, reg_874); |
1311 |
0x1CC000, rtlpriv->reg_874); |
1219 |
rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3), |
1312 |
rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3), |
1220 |
reg_c70); |
1313 |
rtlpriv->reg_c70); |
1221 |
rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL, 0xFF000000, |
1314 |
rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL, 0xFF000000, |
1222 |
reg_85c); |
1315 |
rtlpriv->reg_85c); |
1223 |
rtl_set_bbreg(hw, 0xa74, 0xF000, reg_a74); |
1316 |
rtl_set_bbreg(hw, 0xa74, 0xF000, rtlpriv->reg_a74); |
1224 |
rtl_set_bbreg(hw, 0x818, BIT(28), 0x0); |
1317 |
rtl_set_bbreg(hw, 0x818, BIT(28), 0x0); |
1225 |
} |
1318 |
} |
1226 |
|
1319 |
|
Lines 1236-1241
static void rtl92c_dm_dynamic_bb_powersa
Link Here
|
1236 |
struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); |
1329 |
struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); |
1237 |
struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); |
1330 |
struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); |
1238 |
|
1331 |
|
|
|
1332 |
/* Determine the minimum RSSI */ |
1239 |
if (((mac->link_state == MAC80211_NOLINK)) && |
1333 |
if (((mac->link_state == MAC80211_NOLINK)) && |
1240 |
(rtlpriv->dm.entry_min_undec_sm_pwdb == 0)) { |
1334 |
(rtlpriv->dm.entry_min_undec_sm_pwdb == 0)) { |
1241 |
dm_pstable->rssi_val_min = 0; |
1335 |
dm_pstable->rssi_val_min = 0; |
Lines 1264-1269
static void rtl92c_dm_dynamic_bb_powersa
Link Here
|
1264 |
dm_pstable->rssi_val_min); |
1358 |
dm_pstable->rssi_val_min); |
1265 |
} |
1359 |
} |
1266 |
|
1360 |
|
|
|
1361 |
/* Power Saving for 92C */ |
1267 |
if (IS_92C_SERIAL(rtlhal->version)) |
1362 |
if (IS_92C_SERIAL(rtlhal->version)) |
1268 |
;/* rtl92c_dm_1r_cca(hw); */ |
1363 |
;/* rtl92c_dm_1r_cca(hw); */ |
1269 |
else |
1364 |
else |
Lines 1275-1286
void rtl92c_dm_init(struct ieee80211_hw
Link Here
|
1275 |
struct rtl_priv *rtlpriv = rtl_priv(hw); |
1370 |
struct rtl_priv *rtlpriv = rtl_priv(hw); |
1276 |
|
1371 |
|
1277 |
rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER; |
1372 |
rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER; |
|
|
1373 |
rtlpriv->dm.dm_flag = DYNAMIC_FUNC_DISABLE | DYNAMIC_FUNC_DIG; |
1374 |
rtlpriv->dm.undec_sm_pwdb = -1; |
1375 |
rtlpriv->dm.undec_sm_cck = -1; |
1376 |
rtlpriv->dm.dm_initialgain_enable = true; |
1278 |
rtl92c_dm_diginit(hw); |
1377 |
rtl92c_dm_diginit(hw); |
|
|
1378 |
|
1379 |
rtlpriv->dm.dm_flag |= HAL_DM_HIPWR_DISABLE; |
1279 |
rtl92c_dm_init_dynamic_txpower(hw); |
1380 |
rtl92c_dm_init_dynamic_txpower(hw); |
|
|
1381 |
|
1280 |
rtl92c_dm_init_edca_turbo(hw); |
1382 |
rtl92c_dm_init_edca_turbo(hw); |
1281 |
rtl92c_dm_init_rate_adaptive_mask(hw); |
1383 |
rtl92c_dm_init_rate_adaptive_mask(hw); |
|
|
1384 |
rtlpriv->dm.dm_flag |= DYNAMIC_FUNC_SS; |
1282 |
rtl92c_dm_initialize_txpower_tracking(hw); |
1385 |
rtl92c_dm_initialize_txpower_tracking(hw); |
1283 |
rtl92c_dm_init_dynamic_bb_powersaving(hw); |
1386 |
rtl92c_dm_init_dynamic_bb_powersaving(hw); |
|
|
1387 |
|
1388 |
rtlpriv->dm.ofdm_pkt_cnt = 0; |
1389 |
rtlpriv->dm.dm_rssi_sel = RSSI_DEFAULT; |
1284 |
} |
1390 |
} |
1285 |
EXPORT_SYMBOL(rtl92c_dm_init); |
1391 |
EXPORT_SYMBOL(rtl92c_dm_init); |
1286 |
|
1392 |
|
Lines 1331-1337
void rtl92c_dm_dynamic_txpower(struct ie
Link Here
|
1331 |
} |
1437 |
} |
1332 |
|
1438 |
|
1333 |
if (undec_sm_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL2) { |
1439 |
if (undec_sm_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL2) { |
1334 |
rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1; |
1440 |
rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL2; |
1335 |
RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, |
1441 |
RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, |
1336 |
"TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x0)\n"); |
1442 |
"TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x0)\n"); |
1337 |
} else if ((undec_sm_pwdb < (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3)) && |
1443 |
} else if ((undec_sm_pwdb < (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3)) && |
Lines 1351-1358
void rtl92c_dm_dynamic_txpower(struct ie
Link Here
|
1351 |
"PHY_SetTxPowerLevel8192S() Channel = %d\n", |
1457 |
"PHY_SetTxPowerLevel8192S() Channel = %d\n", |
1352 |
rtlphy->current_channel); |
1458 |
rtlphy->current_channel); |
1353 |
rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel); |
1459 |
rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel); |
|
|
1460 |
if (rtlpriv->dm.dynamic_txhighpower_lvl == |
1461 |
TXHIGHPWRLEVEL_NORMAL) |
1462 |
dm_restorepowerindex(hw); |
1463 |
else if (rtlpriv->dm.dynamic_txhighpower_lvl == |
1464 |
TXHIGHPWRLEVEL_LEVEL1) |
1465 |
dm_writepowerindex(hw, 0x14); |
1466 |
else if (rtlpriv->dm.dynamic_txhighpower_lvl == |
1467 |
TXHIGHPWRLEVEL_LEVEL2) |
1468 |
dm_writepowerindex(hw, 0x10); |
1354 |
} |
1469 |
} |
1355 |
|
|
|
1356 |
rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl; |
1470 |
rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl; |
1357 |
} |
1471 |
} |
1358 |
|
1472 |
|
Lines 1423-1434
u8 rtl92c_bt_rssi_state_change(struct ie
Link Here
|
1423 |
else |
1537 |
else |
1424 |
curr_bt_rssi_state &= (~BT_RSSI_STATE_SPECIAL_LOW); |
1538 |
curr_bt_rssi_state &= (~BT_RSSI_STATE_SPECIAL_LOW); |
1425 |
|
1539 |
|
1426 |
/* Set Tx Power according to BT status. */ |
|
|
1427 |
if (undec_sm_pwdb >= 30) |
1428 |
curr_bt_rssi_state |= BT_RSSI_STATE_TXPOWER_LOW; |
1429 |
else if (undec_sm_pwdb < 25) |
1430 |
curr_bt_rssi_state &= (~BT_RSSI_STATE_TXPOWER_LOW); |
1431 |
|
1432 |
/* Check BT state related to BT_Idle in B/G mode. */ |
1540 |
/* Check BT state related to BT_Idle in B/G mode. */ |
1433 |
if (undec_sm_pwdb < 15) |
1541 |
if (undec_sm_pwdb < 15) |
1434 |
curr_bt_rssi_state |= BT_RSSI_STATE_BG_EDCA_LOW; |
1542 |
curr_bt_rssi_state |= BT_RSSI_STATE_BG_EDCA_LOW; |