Attachment #10172 for bug #5992

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#define RTL_R32(reg)		((unsigned long) readl (ioaddr + (reg)))

enum mac_version {
	RTL_GIGA_MAC_VER_00 = 0x00,	// 8169
	RTL_GIGA_MAC_VER_01 = 0x01,	// 8169S
	RTL_GIGA_MAC_VER_02 = 0x02,	// 8110S
	RTL_GIGA_MAC_VER_03 = 0x03,
	RTL_GIGA_MAC_VER_04 = 0x04,	// 8169SB
	RTL_GIGA_MAC_VER_05 = 0x05,	// 8169SCd
	RTL_GIGA_MAC_VER_06 = 0x06,	// 8169SCe
	RTL_GIGA_MAC_VER_11 = 0x0b,
	RTL_GIGA_MAC_VER_12 = 0x0c,
	RTL_GIGA_MAC_VER_13 = 0x0d,

	u8 mac_version;
	u32 RxConfigMask;	/* Clears the bits supported by this chip */
} rtl_chip_info[] = {
	_R("RTL8169",		RTL_GIGA_MAC_VER_00, 0xff7e1880),
	_R("RTL8169s/8110s",	RTL_GIGA_MAC_VER_01, 0xff7e1880),
	_R("RTL8169s/8110s",	RTL_GIGA_MAC_VER_02, 0xff7e1880),
	_R("RTL8169sb/8110sb",	RTL_GIGA_MAC_VER_03, 0xff7e1880),
	_R("RTL8169sc/8110sc",	RTL_GIGA_MAC_VER_04, 0xff7e1880),
	_R("RTL8169sc/8110sc",	RTL_GIGA_MAC_VER_05, 0xff7e1880),
	_R("RTL8169sc/8110sc",	RTL_GIGA_MAC_VER_06, 0xff7e1880),
	_R("RTL8168b/8111b",	RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
	_R("RTL8168b/8111b",	RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
	_R("RTL8101e",		RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139


enum RTL8169_registers {
	MAC0 = 0,		/* Ethernet hardware address. */
	MAC4 = 4,
	MAR0 = 8,		/* Multicast filter. */
	CounterAddrLow = 0x10,
	CounterAddrHigh = 0x14,

	/* Config1 register p.24 */
	PMEnable	= (1 << 0),	/* Power Management Enable */

	/* Config2 register p. 25 */
	PCI_Clock_66MHz	= 0x01,
	PCI_Clock_33MHz	= 0x00,


	/* Config3 register p.25 */
	MagicPacket	= (1 << 5),	/* Wake up when receives a Magic Packet */
	LinkUp		= (1 << 4),	/* Wake up when the cable connection is re-established */

		{ 0x34000000,	RTL_GIGA_MAC_VER_13 },
		{ 0x30800000,	RTL_GIGA_MAC_VER_14 },
		{ 0x30000000,	RTL_GIGA_MAC_VER_11 },
		{ 0x98000000,	RTL_GIGA_MAC_VER_05 },
		{ 0x18000000,	RTL_GIGA_MAC_VER_05 },
		{ 0x18000000,	RTL_GIGA_MAC_VER_04 },
		{ 0x10000000,	RTL_GIGA_MAC_VER_03 },
		{ 0x04000000,	RTL_GIGA_MAC_VER_02 },
		{ 0x00800000,	RTL_GIGA_MAC_VER_01 },
		{ 0x00000000,	RTL_GIGA_MAC_VER_00 }	/* Catch-all */
	}, *p = mac_info;
	u32 reg;

	reg = RTL_R32(TxConfig) & 0xfc800000;
	while ((reg & p->mask) != p->mask)
		p++;
	tp->mac_version = p->mac_version;

	rtl8169_print_mac_version(tp);
	rtl8169_print_phy_version(tp);

	if (tp->mac_version <= RTL_GIGA_MAC_VER_00)
		return;
	if (tp->phy_version >= RTL_GIGA_PHY_VER_H)
		return;


	/* Shazam ! */

	if (tp->mac_version == RTL_GIGA_MAC_VER_03) {
		mdio_write(ioaddr, 31, 0x0002);
		mdio_write(ioaddr,  1, 0x90d0);
		mdio_write(ioaddr, 31, 0x0000);

	void __iomem *ioaddr = tp->mmio_addr;
	unsigned long timeout = RTL8169_PHY_TIMEOUT;

	assert(tp->mac_version > RTL_GIGA_MAC_VER_00);
	assert(tp->phy_version < RTL_GIGA_PHY_VER_H);

	if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))

	struct rtl8169_private *tp = netdev_priv(dev);
	struct timer_list *timer = &tp->timer;

	if ((tp->mac_version <= RTL_GIGA_MAC_VER_00) ||
	    (tp->phy_version >= RTL_GIGA_PHY_VER_H))
		return;


	struct rtl8169_private *tp = netdev_priv(dev);
	struct timer_list *timer = &tp->timer;

	if ((tp->mac_version <= RTL_GIGA_MAC_VER_00) ||
	    (tp->phy_version >= RTL_GIGA_PHY_VER_H))
		return;


	dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
	RTL_W8(0x82, 0x01);

	if (tp->mac_version < RTL_GIGA_MAC_VER_02) {
		dprintk("Set PCI Latency=0x40\n");
		pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
	}

	pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);

	if (tp->mac_version == RTL_GIGA_MAC_VER_01) {
		dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
		RTL_W8(0x82, 0x01);
		dprintk("Set PHY Reg 0x0bh = 0x00h\n");

		printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
}

static void rtl8169_rar_set(struct rtl8169_private *tp, u8 *addr)
{
	void __iomem *ioaddr = tp->mmio_addr;
	u32 low;
	u32 high;

	low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
	high = addr[4] | (addr[5] << 8);

	RTL_W8(Cfg9346, Cfg9346_Unlock);
	RTL_W32(MAC0, low);
	RTL_W32(MAC4, high);
	RTL_W8(Cfg9346, Cfg9346_Lock);
}

static int rtl8169_set_mac_address(struct net_device *dev, void *p)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	struct sockaddr *addr = p;

	if (!is_valid_ether_addr(addr->sa_data))
		return -EADDRNOTAVAIL;

	memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);

	rtl8169_rar_set(tp, dev->dev_addr);

	return 0;
}

static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
{
	struct rtl8169_private *tp = netdev_priv(dev);

	dev->irq = pdev->irq;
	dev->base_addr = (unsigned long) ioaddr;
	dev->change_mtu = rtl8169_change_mtu;
	dev->set_mac_address = rtl8169_set_mac_address;

#ifdef CONFIG_R8169_NAPI
	dev->poll = rtl8169_poll;

		(InterFrameGap << TxInterFrameGapShift));
}

static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
{
	struct {
		u32 mac_version;
		u32 clk66;
		u32 val;
	} cfg2_info [] = {
		{ RTL_GIGA_MAC_VER_05, 0, 0x000fff00 },
		{ RTL_GIGA_MAC_VER_05, 1, 0x000fffff },
		{ RTL_GIGA_MAC_VER_06, 0, 0x00ffffff },
		{ RTL_GIGA_MAC_VER_06, 1, 0x00ffff00 }
	}, *p = cfg2_info;
	unsigned int i;
	u32 clk66;

	clk66 = RTL_R8(Config2) & PCI_Clock_66MHz;
	for (i = 0; i < ARRAY_SIZE(cfg2_info); i++) {
		if ((p->mac_version == mac_version) && (p->clk66 == clk66)) {
			RTL_W32(0x7c, p->val);
			break;
		}
	}
}

static bool rtl8169_plain_old_8169(unsigned int mac_version)
{
	return ((mac_version == RTL_GIGA_MAC_VER_00) ||
		(mac_version == RTL_GIGA_MAC_VER_01) ||
		(mac_version == RTL_GIGA_MAC_VER_02) ||
		(mac_version == RTL_GIGA_MAC_VER_03) || // FIXME: remove ?
		(mac_version == RTL_GIGA_MAC_VER_04) ||
		(mac_version == RTL_GIGA_MAC_VER_05) ||
		(mac_version == RTL_GIGA_MAC_VER_06)) ? true : false;
}

static void rtl8169_hw_start(struct net_device *dev)
{
	struct rtl8169_private *tp = netdev_priv(dev);

		msleep_interruptible(1);
	}

	if (tp->mac_version == RTL_GIGA_MAC_VER_04)
		RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
		pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
	}

	if (tp->mac_version == RTL_GIGA_MAC_VER_13) {
		pci_write_config_word(pdev, 0x68, 0x00);

	}

	/* Undocumented stuff. */
	if (tp->mac_version == RTL_GIGA_MAC_VER_04) {
		/* Realtek's r1000_n.c driver uses '&& 0x01' here. Well... */
		if ((RTL_R8(Config2) & 0x07) & 0x01)
			RTL_W32(0x7c, 0x0007ffff);

	}

	RTL_W8(Cfg9346, Cfg9346_Unlock);

	if (rtl8169_plain_old_8169(tp->mac_version))
	    (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
	    (tp->mac_version == RTL_GIGA_MAC_VER_04))
		RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);

	RTL_W8(EarlyTxThres, EarlyTxThld);

	/* Low hurts. Let's disable the filtering. */
	RTL_W16(RxMaxSize, 16383);

	if (rtl8169_plain_old_8169(tp->mac_version))
	    (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
	    (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
	    (tp->mac_version == RTL_GIGA_MAC_VER_04))
		rtl8169_set_rx_tx_config_registers(tp);

	cmd = RTL_R16(CPlusCmd);


	tp->cp_cmd |= cmd | PCIMulRW;

	rtl8169_set_magic_reg(ioaddr, tp->mac_version);

	if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
	    (tp->mac_version == RTL_GIGA_MAC_VER_02)) {
		dprintk(KERN_INFO PFX "Set MAC Reg C+CR Offset 0xE0. "
			"Bit-3 and bit-14 MUST be 1\n");
		tp->cp_cmd |= (1 << 14);

	RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr >> 32));
	RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr & DMA_32BIT_MASK));

	if (!rtl8169_plain_old_8169(tp->mac_version)) {
	    (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
	    (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
	    (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
		RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
		rtl8169_set_rx_tx_config_registers(tp);
	}

	/* Enable all known interrupts by setting the interrupt mask. */
	RTL_W16(IntrMask, rtl8169_intr_mask);

	if (rtl8169_plain_old_8169(tp->mac_version))
		RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);

	netif_start_queue(dev);
}


			tp->stats.rx_bytes += pkt_size;
			tp->stats.rx_packets++;
		}

		/* Work around for AMD plateform. */
		if ((desc->opts2 & 0xfffe000) &&
		    (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
			desc->opts2 = 0;
			cur_rx++;
		}

	}

	count = cur_rx - tp->cur_rx;
- 

Return to bug 5992

Lines 150-160 static const int multicast_filter_limit = 32; Link Here

(-)a/drivers/net/r8169.c (-39 / +121 lines)
150	#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))	150	#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
151		151
152	enum mac_version {	152	enum mac_version {
153	RTL_GIGA_MAC_VER_01 = 0x00,	153	RTL_GIGA_MAC_VER_00 = 0x00, // 8169
154	RTL_GIGA_MAC_VER_02 = 0x01,	154	RTL_GIGA_MAC_VER_01 = 0x01, // 8169S
155	RTL_GIGA_MAC_VER_03 = 0x02,	155	RTL_GIGA_MAC_VER_02 = 0x02, // 8110S
156	RTL_GIGA_MAC_VER_04 = 0x03,	156	RTL_GIGA_MAC_VER_03 = 0x03,
157	RTL_GIGA_MAC_VER_05 = 0x04,	157	RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
		158	RTL_GIGA_MAC_VER_05 = 0x05, // 8169SCd
		159	RTL_GIGA_MAC_VER_06 = 0x06, // 8169SCe
158	RTL_GIGA_MAC_VER_11 = 0x0b,	160	RTL_GIGA_MAC_VER_11 = 0x0b,
159	RTL_GIGA_MAC_VER_12 = 0x0c,	161	RTL_GIGA_MAC_VER_12 = 0x0c,
160	RTL_GIGA_MAC_VER_13 = 0x0d,	162	RTL_GIGA_MAC_VER_13 = 0x0d,
Lines 179-189 static const struct { Link Here
179	u8 mac_version;	181	u8 mac_version;
180	u32 RxConfigMask; /* Clears the bits supported by this chip */	182	u32 RxConfigMask; /* Clears the bits supported by this chip */
181	} rtl_chip_info[] = {	183	} rtl_chip_info[] = {
182	_R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880),	184	_R("RTL8169", RTL_GIGA_MAC_VER_00, 0xff7e1880),
		185	_R("RTL8169s/8110s", RTL_GIGA_MAC_VER_01, 0xff7e1880),
183	_R("RTL8169s/8110s", RTL_GIGA_MAC_VER_02, 0xff7e1880),	186	_R("RTL8169s/8110s", RTL_GIGA_MAC_VER_02, 0xff7e1880),
184	_R("RTL8169s/8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880),	187	_R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_03, 0xff7e1880),
185	_R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880),	188	_R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_04, 0xff7e1880),
186	_R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880),	189	_R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880),
		190	_R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880),
187	_R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E	191	_R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
188	_R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E	192	_R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
189	_R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139	193	_R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
Lines 231-236 static struct { Link Here
231		235
232	enum RTL8169_registers {	236	enum RTL8169_registers {
233	MAC0 = 0, /* Ethernet hardware address. */	237	MAC0 = 0, /* Ethernet hardware address. */
		238	MAC4 = 4,
234	MAR0 = 8, /* Multicast filter. */	239	MAR0 = 8, /* Multicast filter. */
235	CounterAddrLow = 0x10,	240	CounterAddrLow = 0x10,
236	CounterAddrHigh = 0x14,	241	CounterAddrHigh = 0x14,
Lines 322-327 enum RTL8169_register_content { Link Here
322	/* Config1 register p.24 */	327	/* Config1 register p.24 */
323	PMEnable = (1 << 0), /* Power Management Enable */	328	PMEnable = (1 << 0), /* Power Management Enable */
324		329
		330	/* Config2 register p. 25 */
		331	PCI_Clock_66MHz = 0x01,
		332	PCI_Clock_33MHz = 0x00,
		333
		334
325	/* Config3 register p.25 */	335	/* Config3 register p.25 */
326	MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */	336	MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
327	LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */	337	LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
Lines 1172-1186 static void rtl8169_get_mac_version(struct rtl8169_private tp, void __iomem io Link Here
1172	{ 0x34000000, RTL_GIGA_MAC_VER_13 },	1182	{ 0x34000000, RTL_GIGA_MAC_VER_13 },
1173	{ 0x30800000, RTL_GIGA_MAC_VER_14 },	1183	{ 0x30800000, RTL_GIGA_MAC_VER_14 },
1174	{ 0x30000000, RTL_GIGA_MAC_VER_11 },	1184	{ 0x30000000, RTL_GIGA_MAC_VER_11 },
		1185	{ 0x98000000, RTL_GIGA_MAC_VER_05 },
1175	{ 0x18000000, RTL_GIGA_MAC_VER_05 },	1186	{ 0x18000000, RTL_GIGA_MAC_VER_05 },
1176	{ 0x10000000, RTL_GIGA_MAC_VER_04 },	1187	{ 0x18000000, RTL_GIGA_MAC_VER_04 },
1177	{ 0x04000000, RTL_GIGA_MAC_VER_03 },	1188	{ 0x10000000, RTL_GIGA_MAC_VER_03 },
1178	{ 0x00800000, RTL_GIGA_MAC_VER_02 },	1189	{ 0x04000000, RTL_GIGA_MAC_VER_02 },
1179	{ 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */	1190	{ 0x00800000, RTL_GIGA_MAC_VER_01 },
		1191	{ 0x00000000, RTL_GIGA_MAC_VER_00 } /* Catch-all */
1180	}, *p = mac_info;	1192	}, *p = mac_info;
1181	u32 reg;	1193	u32 reg;
1182		1194
1183	reg = RTL_R32(TxConfig) & 0x7c800000;	1195	reg = RTL_R32(TxConfig) & 0xfc800000;
1184	while ((reg & p->mask) != p->mask)	1196	while ((reg & p->mask) != p->mask)
1185	p++;	1197	p++;
1186	tp->mac_version = p->mac_version;	1198	tp->mac_version = p->mac_version;
Lines 1273-1279 static void rtl8169_hw_phy_config(struct net_device *dev) Link Here
1273	rtl8169_print_mac_version(tp);	1285	rtl8169_print_mac_version(tp);
1274	rtl8169_print_phy_version(tp);	1286	rtl8169_print_phy_version(tp);
1275		1287
1276	if (tp->mac_version <= RTL_GIGA_MAC_VER_01)	1288	if (tp->mac_version <= RTL_GIGA_MAC_VER_00)
1277	return;	1289	return;
1278	if (tp->phy_version >= RTL_GIGA_PHY_VER_H)	1290	if (tp->phy_version >= RTL_GIGA_PHY_VER_H)
1279	return;	1291	return;
Lines 1283-1289 static void rtl8169_hw_phy_config(struct net_device *dev) Link Here
1283		1295
1284	/* Shazam ! */	1296	/* Shazam ! */
1285		1297
1286	if (tp->mac_version == RTL_GIGA_MAC_VER_04) {	1298	if (tp->mac_version == RTL_GIGA_MAC_VER_03) {
1287	mdio_write(ioaddr, 31, 0x0002);	1299	mdio_write(ioaddr, 31, 0x0002);
1288	mdio_write(ioaddr, 1, 0x90d0);	1300	mdio_write(ioaddr, 1, 0x90d0);
1289	mdio_write(ioaddr, 31, 0x0000);	1301	mdio_write(ioaddr, 31, 0x0000);
Lines 1317-1323 static void rtl8169_phy_timer(unsigned long __opaque) Link Here
1317	void __iomem *ioaddr = tp->mmio_addr;	1329	void __iomem *ioaddr = tp->mmio_addr;
1318	unsigned long timeout = RTL8169_PHY_TIMEOUT;	1330	unsigned long timeout = RTL8169_PHY_TIMEOUT;
1319		1331
1320	assert(tp->mac_version > RTL_GIGA_MAC_VER_01);	1332	assert(tp->mac_version > RTL_GIGA_MAC_VER_00);
1321	assert(tp->phy_version < RTL_GIGA_PHY_VER_H);	1333	assert(tp->phy_version < RTL_GIGA_PHY_VER_H);
1322		1334
1323	if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))	1335	if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
Lines 1353-1359 static inline void rtl8169_delete_timer(struct net_device *dev) Link Here
1353	struct rtl8169_private *tp = netdev_priv(dev);	1365	struct rtl8169_private *tp = netdev_priv(dev);
1354	struct timer_list *timer = &tp->timer;	1366	struct timer_list *timer = &tp->timer;
1355		1367
1356	if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) \|\|	1368	if ((tp->mac_version <= RTL_GIGA_MAC_VER_00) \|\|
1357	(tp->phy_version >= RTL_GIGA_PHY_VER_H))	1369	(tp->phy_version >= RTL_GIGA_PHY_VER_H))
1358	return;	1370	return;
1359		1371
Lines 1365-1371 static inline void rtl8169_request_timer(struct net_device *dev) Link Here
1365	struct rtl8169_private *tp = netdev_priv(dev);	1377	struct rtl8169_private *tp = netdev_priv(dev);
1366	struct timer_list *timer = &tp->timer;	1378	struct timer_list *timer = &tp->timer;
1367		1379
1368	if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) \|\|	1380	if ((tp->mac_version <= RTL_GIGA_MAC_VER_00) \|\|
1369	(tp->phy_version >= RTL_GIGA_PHY_VER_H))	1381	(tp->phy_version >= RTL_GIGA_PHY_VER_H))
1370	return;	1382	return;
1371		1383
Lines 1432-1443 static void rtl8169_init_phy(struct net_device dev, struct rtl8169_private tp) Link Here
1432	dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");	1444	dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1433	RTL_W8(0x82, 0x01);	1445	RTL_W8(0x82, 0x01);
1434		1446
1435	if (tp->mac_version < RTL_GIGA_MAC_VER_03) {	1447	if (tp->mac_version < RTL_GIGA_MAC_VER_02) {
1436	dprintk("Set PCI Latency=0x40\n");	1448	dprintk("Set PCI Latency=0x40\n");
1437	pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);	1449	pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1438	}	1450	}
1439		1451
1440	if (tp->mac_version == RTL_GIGA_MAC_VER_02) {	1452	pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
		1453
		1454	if (tp->mac_version == RTL_GIGA_MAC_VER_01) {
1441	dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");	1455	dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1442	RTL_W8(0x82, 0x01);	1456	RTL_W8(0x82, 0x01);
1443	dprintk("Set PHY Reg 0x0bh = 0x00h\n");	1457	dprintk("Set PHY Reg 0x0bh = 0x00h\n");
Lines 1454-1459 static void rtl8169_init_phy(struct net_device dev, struct rtl8169_private tp) Link Here
1454	printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);	1468	printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1455	}	1469	}
1456		1470
		1471	static void rtl8169_rar_set(struct rtl8169_private tp, u8 addr)
		1472	{
		1473	void __iomem *ioaddr = tp->mmio_addr;
		1474	u32 low;
		1475	u32 high;
		1476
		1477	low = addr[0] \| (addr[1] << 8) \| (addr[2] << 16) \| (addr[3] << 24);
		1478	high = addr[4] \| (addr[5] << 8);
		1479
		1480	RTL_W8(Cfg9346, Cfg9346_Unlock);
		1481	RTL_W32(MAC0, low);
		1482	RTL_W32(MAC4, high);
		1483	RTL_W8(Cfg9346, Cfg9346_Lock);
		1484	}
		1485
		1486	static int rtl8169_set_mac_address(struct net_device dev, void p)
		1487	{
		1488	struct rtl8169_private *tp = netdev_priv(dev);
		1489	struct sockaddr *addr = p;
		1490
		1491	if (!is_valid_ether_addr(addr->sa_data))
		1492	return -EADDRNOTAVAIL;
		1493
		1494	memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
		1495
		1496	rtl8169_rar_set(tp, dev->dev_addr);
		1497
		1498	return 0;
		1499	}
		1500
1457	static int rtl8169_ioctl(struct net_device dev, struct ifreq ifr, int cmd)	1501	static int rtl8169_ioctl(struct net_device dev, struct ifreq ifr, int cmd)
1458	{	1502	{
1459	struct rtl8169_private *tp = netdev_priv(dev);	1503	struct rtl8169_private *tp = netdev_priv(dev);
Lines 1665-1670 rtl8169_init_one(struct pci_dev pdev, const struct pci_device_id ent) Link Here
1665	dev->irq = pdev->irq;	1709	dev->irq = pdev->irq;
1666	dev->base_addr = (unsigned long) ioaddr;	1710	dev->base_addr = (unsigned long) ioaddr;
1667	dev->change_mtu = rtl8169_change_mtu;	1711	dev->change_mtu = rtl8169_change_mtu;
		1712	dev->set_mac_address = rtl8169_set_mac_address;
1668		1713
1669	#ifdef CONFIG_R8169_NAPI	1714	#ifdef CONFIG_R8169_NAPI
1670	dev->poll = rtl8169_poll;	1715	dev->poll = rtl8169_poll;
Lines 1825-1830 static void rtl8169_set_rx_tx_config_registers(struct rtl8169_private *tp) Link Here
1825	(InterFrameGap << TxInterFrameGapShift));	1870	(InterFrameGap << TxInterFrameGapShift));
1826	}	1871	}
1827		1872
		1873	static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
		1874	{
		1875	struct {
		1876	u32 mac_version;
		1877	u32 clk66;
		1878	u32 val;
		1879	} cfg2_info [] = {
		1880	{ RTL_GIGA_MAC_VER_05, 0, 0x000fff00 },
		1881	{ RTL_GIGA_MAC_VER_05, 1, 0x000fffff },
		1882	{ RTL_GIGA_MAC_VER_06, 0, 0x00ffffff },
		1883	{ RTL_GIGA_MAC_VER_06, 1, 0x00ffff00 }
		1884	}, *p = cfg2_info;
		1885	unsigned int i;
		1886	u32 clk66;
		1887
		1888	clk66 = RTL_R8(Config2) & PCI_Clock_66MHz;
		1889	for (i = 0; i < ARRAY_SIZE(cfg2_info); i++) {
		1890	if ((p->mac_version == mac_version) && (p->clk66 == clk66)) {
		1891	RTL_W32(0x7c, p->val);
		1892	break;
		1893	}
		1894	}
		1895	}
		1896
		1897	static bool rtl8169_plain_old_8169(unsigned int mac_version)
		1898	{
		1899	return ((mac_version == RTL_GIGA_MAC_VER_00) \|\|
		1900	(mac_version == RTL_GIGA_MAC_VER_01) \|\|
		1901	(mac_version == RTL_GIGA_MAC_VER_02) \|\|
		1902	(mac_version == RTL_GIGA_MAC_VER_03) \|\| // FIXME: remove ?
		1903	(mac_version == RTL_GIGA_MAC_VER_04) \|\|
		1904	(mac_version == RTL_GIGA_MAC_VER_05) \|\|
		1905	(mac_version == RTL_GIGA_MAC_VER_06)) ? true : false;
		1906	}
		1907
1828	static void rtl8169_hw_start(struct net_device *dev)	1908	static void rtl8169_hw_start(struct net_device *dev)
1829	{	1909	{
1830	struct rtl8169_private *tp = netdev_priv(dev);	1910	struct rtl8169_private *tp = netdev_priv(dev);
Lines 1843-1852 static void rtl8169_hw_start(struct net_device *dev) Link Here
1843	msleep_interruptible(1);	1923	msleep_interruptible(1);
1844	}	1924	}
1845		1925
1846	if (tp->mac_version == RTL_GIGA_MAC_VER_05) {	1926	if (tp->mac_version == RTL_GIGA_MAC_VER_04)
1847	RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) \| PCIMulRW);	1927	RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) \| PCIMulRW);
1848	pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
1849	}
1850		1928
1851	if (tp->mac_version == RTL_GIGA_MAC_VER_13) {	1929	if (tp->mac_version == RTL_GIGA_MAC_VER_13) {
1852	pci_write_config_word(pdev, 0x68, 0x00);	1930	pci_write_config_word(pdev, 0x68, 0x00);
Lines 1854-1860 static void rtl8169_hw_start(struct net_device *dev) Link Here
1854	}	1932	}
1855		1933
1856	/* Undocumented stuff. */	1934	/* Undocumented stuff. */
1857	if (tp->mac_version == RTL_GIGA_MAC_VER_05) {	1935	if (tp->mac_version == RTL_GIGA_MAC_VER_04) {
1858	/* Realtek's r1000_n.c driver uses '&& 0x01' here. Well... */	1936	/* Realtek's r1000_n.c driver uses '&& 0x01' here. Well... */
1859	if ((RTL_R8(Config2) & 0x07) & 0x01)	1937	if ((RTL_R8(Config2) & 0x07) & 0x01)
1860	RTL_W32(0x7c, 0x0007ffff);	1938	RTL_W32(0x7c, 0x0007ffff);
Lines 1867-1876 static void rtl8169_hw_start(struct net_device *dev) Link Here
1867	}	1945	}
1868		1946
1869	RTL_W8(Cfg9346, Cfg9346_Unlock);	1947	RTL_W8(Cfg9346, Cfg9346_Unlock);
1870	if ((tp->mac_version == RTL_GIGA_MAC_VER_01) \|\|	1948
1871	(tp->mac_version == RTL_GIGA_MAC_VER_02) \|\|	1949	if (rtl8169_plain_old_8169(tp->mac_version))
1872	(tp->mac_version == RTL_GIGA_MAC_VER_03) \|\|
1873	(tp->mac_version == RTL_GIGA_MAC_VER_04))
1874	RTL_W8(ChipCmd, CmdTxEnb \| CmdRxEnb);	1950	RTL_W8(ChipCmd, CmdTxEnb \| CmdRxEnb);
1875		1951
1876	RTL_W8(EarlyTxThres, EarlyTxThld);	1952	RTL_W8(EarlyTxThres, EarlyTxThld);
Lines 1878-1887 static void rtl8169_hw_start(struct net_device *dev) Link Here
1878	/* Low hurts. Let's disable the filtering. */	1954	/* Low hurts. Let's disable the filtering. */
1879	RTL_W16(RxMaxSize, 16383);	1955	RTL_W16(RxMaxSize, 16383);
1880		1956
1881	if ((tp->mac_version == RTL_GIGA_MAC_VER_01) \|\|	1957	if (rtl8169_plain_old_8169(tp->mac_version))
1882	(tp->mac_version == RTL_GIGA_MAC_VER_02) \|\|
1883	(tp->mac_version == RTL_GIGA_MAC_VER_03) \|\|
1884	(tp->mac_version == RTL_GIGA_MAC_VER_04))
1885	rtl8169_set_rx_tx_config_registers(tp);	1958	rtl8169_set_rx_tx_config_registers(tp);
1886		1959
1887	cmd = RTL_R16(CPlusCmd);	1960	cmd = RTL_R16(CPlusCmd);
Lines 1889-1896 static void rtl8169_hw_start(struct net_device *dev) Link Here
1889		1962
1890	tp->cp_cmd \|= cmd \| PCIMulRW;	1963	tp->cp_cmd \|= cmd \| PCIMulRW;
1891		1964
1892	if ((tp->mac_version == RTL_GIGA_MAC_VER_02) \|\|	1965	rtl8169_set_magic_reg(ioaddr, tp->mac_version);
1893	(tp->mac_version == RTL_GIGA_MAC_VER_03)) {	1966
		1967	if ((tp->mac_version == RTL_GIGA_MAC_VER_01) \|\|
		1968	(tp->mac_version == RTL_GIGA_MAC_VER_02)) {
1894	dprintk(KERN_INFO PFX "Set MAC Reg C+CR Offset 0xE0. "	1969	dprintk(KERN_INFO PFX "Set MAC Reg C+CR Offset 0xE0. "
1895	"Bit-3 and bit-14 MUST be 1\n");	1970	"Bit-3 and bit-14 MUST be 1\n");
1896	tp->cp_cmd \|= (1 << 14);	1971	tp->cp_cmd \|= (1 << 14);
Lines 1914-1923 static void rtl8169_hw_start(struct net_device *dev) Link Here
1914	RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr >> 32));	1989	RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr >> 32));
1915	RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr & DMA_32BIT_MASK));	1990	RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr & DMA_32BIT_MASK));
1916		1991
1917	if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&	1992	if (!rtl8169_plain_old_8169(tp->mac_version)) {
1918	(tp->mac_version != RTL_GIGA_MAC_VER_02) &&
1919	(tp->mac_version != RTL_GIGA_MAC_VER_03) &&
1920	(tp->mac_version != RTL_GIGA_MAC_VER_04)) {
1921	RTL_W8(ChipCmd, CmdTxEnb \| CmdRxEnb);	1993	RTL_W8(ChipCmd, CmdTxEnb \| CmdRxEnb);
1922	rtl8169_set_rx_tx_config_registers(tp);	1994	rtl8169_set_rx_tx_config_registers(tp);
1923	}	1995	}
Lines 1937-1942 static void rtl8169_hw_start(struct net_device *dev) Link Here
1937	/* Enable all known interrupts by setting the interrupt mask. */	2009	/* Enable all known interrupts by setting the interrupt mask. */
1938	RTL_W16(IntrMask, rtl8169_intr_mask);	2010	RTL_W16(IntrMask, rtl8169_intr_mask);
1939		2011
		2012	if (rtl8169_plain_old_8169(tp->mac_version))
		2013	RTL_W8(ChipCmd, CmdTxEnb \| CmdRxEnb);
		2014
1940	netif_start_queue(dev);	2015	netif_start_queue(dev);
1941	}	2016	}
1942		2017
Lines 2582-2587 rtl8169_rx_interrupt(struct net_device dev, struct rtl8169_private tp, Link Here
2582	tp->stats.rx_bytes += pkt_size;	2657	tp->stats.rx_bytes += pkt_size;
2583	tp->stats.rx_packets++;	2658	tp->stats.rx_packets++;
2584	}	2659	}
		2660
		2661	/* Work around for AMD plateform. */
		2662	if ((desc->opts2 & 0xfffe000) &&
		2663	(tp->mac_version == RTL_GIGA_MAC_VER_05)) {
		2664	desc->opts2 = 0;
		2665	cur_rx++;
		2666	}
		2667
2585	}	2668	}
2586		2669
2587	count = cur_rx - tp->cur_rx;	2670	count = cur_rx - tp->cur_rx;
2588	-