Bug 8542 - possibly incorrect cache sizing.
Summary: possibly incorrect cache sizing.
Status: REJECTED INVALID
Alias: None
Product: Platform Specific/Hardware
Classification: Unclassified
Component: x86-64 (show other bugs)
Hardware: i386 Linux
: P2 normal
Assignee: Andi Kleen
URL:
Keywords:
Depends on:
Blocks:
 
Reported: 2007-05-26 18:05 UTC by Alexandre Correa
Modified: 2007-08-23 18:05 UTC (History)
1 user (show)

See Also:
Kernel Version: 2.6.21.3
Subsystem:
Regression: ---
Bisected commit-id:


Attachments

Description Alexandre Correa 2007-05-26 18:05:12 UTC
Most recent kernel where this bug did *NOT* occur:
Distribution: Centos 5.0 x86_64
Hardware Environment: Dell Power edge 1495
Software Environment:
Problem Description: I recompiled kernel 2.6.21.3 to use "AMD OPTERON", my
porcessors have 2MB of L2 cache.. but kernel detecting only 1MB !!


Checking aperture...
CPU 0: aperture @ f4000000 size 64 MB
Memory: 4119148k/4718592k available (3120k kernel code, 73716k reserved, 1372k
data, 344k init)
Calibrating delay using timer specific routine.. 3602.09 BogoMIPS (lpj=1801046)
Security Framework v1.0.0 initialized
SELinux:  Initializing.
SELinux:  Starting in permissive mode
selinux_register_security:  Registering secondary module capability
Capability LSM initialized as secondary
Mount-cache hash table entries: 256
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
CPU: L2 Cache: 1024K (64 bytes/line)
CPU 0/0 -> Node 0
CPU: Physical Processor ID: 0
CPU: Processor Core ID: 0
SMP alternatives: switching to UP code
ACPI: Core revision 20070126
Using local APIC timer interrupts.
result 12500443
Detected 12.500 MHz APIC timer.
SMP alternatives: switching to SMP code
Booting processor 1/2 APIC 0x1
Initializing CPU#1
Calibrating delay using timer specific routine.. 3600.16 BogoMIPS (lpj=1800082)
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
CPU: L2 Cache: 1024K (64 bytes/line)
CPU 1/1 -> Node 0
CPU: Physical Processor ID: 0
CPU: Processor Core ID: 1
Dual-Core AMD Opteron(tm) Processor 2210 stepping 02
Brought up 2 CPUs


cat /proc/cpuinfo

[root@maresia ~]# cat /proc/cpuinfo
processor       : 0
vendor_id       : AuthenticAMD
cpu family      : 15
model           : 65
model name      : Dual-Core AMD Opteron(tm) Processor 2210
stepping        : 2
cpu MHz         : 1800.063
cache size      : 1024 KB
physical id     : 0
siblings        : 2
core id         : 0
cpu cores       : 2
fpu             : yes
fpu_exception   : yes
cpuid level     : 1
wp              : yes
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov
pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt rdtscp lm
3dnowext 3dnow pni cx16 lahf_lm cmp_legacy svm extapic cr8_legacy
bogomips        : 3602.09
TLB size        : 1024 4K pages
clflush size    : 64
cache_alignment : 64
address sizes   : 40 bits physical, 48 bits virtual
power management: ts fid vid ttp tm stc

processor       : 1
vendor_id       : AuthenticAMD
cpu family      : 15
model           : 65
model name      : Dual-Core AMD Opteron(tm) Processor 2210
stepping        : 2
cpu MHz         : 1800.063
cache size      : 1024 KB
physical id     : 0
siblings        : 2
core id         : 1
cpu cores       : 2
fpu             : yes
fpu_exception   : yes
cpuid level     : 1
wp              : yes
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov
pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt rdtscp lm
3dnowext 3dnow pni cx16 lahf_lm cmp_legacy svm extapic cr8_legacy
bogomips        : 3600.16
TLB size        : 1024 4K pages
clflush size    : 64
cache_alignment : 64
address sizes   : 40 bits physical, 48 bits virtual
power management: ts fid vid ttp tm stc



Steps to reproduce:
dmesg
Comment 1 Dave Jones 2007-06-05 23:48:55 UTC
This value is read directly from the CPU, so it's unlikely to be incorrect.
What does x86info -c say ?

You can get x86info from http://www.codemonkey.org.uk/projects/x86info
Comment 2 Andi Kleen 2007-06-06 02:56:52 UTC
Each core has 1MB of cache on its own which is correctly reported -> INVALID
Comment 3 Alexandre Correa 2007-06-06 04:18:30 UTC
humm.. i think the affirmation of Andi Kleen is true...

on the boot, the motherboard report that processor has 2MB of L2 CACHE... i
don

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