Hey, I was glad to see bug 4401 fixed C2 and C3 not working on some SMP Intel processors and chipsets. However it needs to be extended to work with AMD SMP processors such as the Athlon MP series and 760 MPX chipset. There exists a patch (merged in 2.4) to do this but as a standalone driver and not as part of the ACPI subsystem. The current C2/C3 patch is available here: http://www.sommrey.de/amd76x_pm/ I have a Tyan Tiger MPX motherboard S2466N, BIOS revision 4.06. I'll happily supply the DSDT etc. if needed. I notice that upto C8 (!) is supported by these processors according to /proc/acpi..../info Thanks for all the great work on ACPI!
Interesting patch, but it is a chip-set specific driver, not generic ACPI code, or even related to the ACPI sub-system. If the BIOS really supports SMP C2 and C3 on these systems, then there should not be a chip-set specific driver necessary. Please make sure you've got the latest BIOS for your board and attach the output from acpidump, available in pmtools here: http://ftp.kernel.org/pub/linux/kernel/people/lenb/acpi/utils/ note also, that the C8 thing it the Linux limit, corresponding the a simple array size, and does not reflect a hardware limit. Please paste in the output from /proc/acpi/processor/<pick a cpu>/power and lets see what ACPI thinks of what this board offers.
It thinks C1 is possible! stuart@strr:~$ cat /proc/acpi/processor/CPU0/power active state: C1 max_cstate: C8 bus master activity: 00000000 states: *C1: type[C1] promotion[--] demotion[--] latency[000] usage[00005129]
Created attachment 6298 [details] "acpidump -o acpidump.txt" acpidump as requested.
BIOS sets C2 and C3 latency to 0x65 (101) and 0x3e9 (1001) respectively, or greater than allowed max latency for those states -- 100 and 1000. This is used to mark these states as *disabled*. Closing the bug as INVALID